series_detection.fit.qmsg

FPGA实验：用于检测输入的二进制系列

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.508 ns register register " "Info: Estimated most critical path is register to register delay of 4.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state:inst1\|cnt\[2\] 1 REG LAB_X14_Y12 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y12; Fanout = 9; REG Node = 'state:inst1\|cnt\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { state:inst1|cnt[2] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.275 ns) 1.108 ns state:inst1\|Mux0~130 2 COMB LAB_X15_Y14 1 " "Info: 2: + IC(0.833 ns) + CELL(0.275 ns) = 1.108 ns; Loc. = LAB_X15_Y14; Fanout = 1; COMB Node = 'state:inst1\|Mux0~130'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.108 ns" { state:inst1|cnt[2] state:inst1|Mux0~130 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.271 ns) 1.669 ns state:inst1\|Mux0~131 3 COMB LAB_X15_Y14 1 " "Info: 3: + IC(0.290 ns) + CELL(0.271 ns) = 1.669 ns; Loc. = LAB_X15_Y14; Fanout = 1; COMB Node = 'state:inst1\|Mux0~131'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.561 ns" { state:inst1|Mux0~130 state:inst1|Mux0~131 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.910 ns) + CELL(0.150 ns) 2.729 ns state:inst1\|Mux0~132 4 COMB LAB_X15_Y12 2 " "Info: 4: + IC(0.910 ns) + CELL(0.150 ns) = 2.729 ns; Loc. = LAB_X15_Y12; Fanout = 2; COMB Node = 'state:inst1\|Mux0~132'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.060 ns" { state:inst1|Mux0~131 state:inst1|Mux0~132 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.420 ns) 3.294 ns state:inst1\|Mux0~133 5 COMB LAB_X15_Y12 5 " "Info: 5: + IC(0.145 ns) + CELL(0.420 ns) = 3.294 ns; Loc. = LAB_X15_Y12; Fanout = 5; COMB Node = 'state:inst1\|Mux0~133'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { state:inst1|Mux0~132 state:inst1|Mux0~133 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 3.859 ns state:inst1\|Mux4~310 6 COMB LAB_X15_Y12 2 " "Info: 6: + IC(0.415 ns) + CELL(0.150 ns) = 3.859 ns; Loc. = LAB_X15_Y12; Fanout = 2; COMB Node = 'state:inst1\|Mux4~310'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { state:inst1|Mux0~133 state:inst1|Mux4~310 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 4.424 ns state:inst1\|Mux3~284 7 COMB LAB_X15_Y12 1 " "Info: 7: + IC(0.415 ns) + CELL(0.150 ns) = 4.424 ns; Loc. = LAB_X15_Y12; Fanout = 1; COMB Node = 'state:inst1\|Mux3~284'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { state:inst1|Mux4~310 state:inst1|Mux3~284 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.508 ns state:inst1\|next_state\[6\] 8 REG LAB_X15_Y12 1 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 4.508 ns; Loc. = LAB_X15_Y12; Fanout = 1; REG Node = 'state:inst1\|next_state\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { state:inst1|Mux3~284 state:inst1|next_state[6] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 33.27 % ) " "Info: Total cell delay = 1.500 ns ( 33.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.008 ns ( 66.73 % ) " "Info: Total interconnect delay = 3.008 ns ( 66.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.508 ns" { state:inst1|cnt[2] state:inst1|Mux0~130 state:inst1|Mux0~131 state:inst1|Mux0~132 state:inst1|Mux0~133 state:inst1|Mux4~310 state:inst1|Mux3~284 state:inst1|next_state[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x11_y12 x21_y23 " "Info: The peak interconnect region extends from location x11_y12 to location x21_y23" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "z 0 " "Info: Pin \"z\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 31 15:20:13 2008 " "Info: Processing ended: Fri Oct 31 15:20:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.fit.smsg " "Info: Generated suppressed messages file E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}