series_detection.sim.rpt

FPGA实验：用于检测输入的二进制系列

; |series_detection|series:inst|cntfrq0[8]  ; |series_detection|series:inst|cntfrq0[8]  ; regout           ;
; |series_detection|series:inst|cntfrq1[3]  ; |series_detection|series:inst|cntfrq1[3]  ; regout           ;
; |series_detection|series:inst|cntfrq1[0]  ; |series_detection|series:inst|cntfrq1[0]  ; regout           ;
; |series_detection|series:inst|cntfrq1[1]  ; |series_detection|series:inst|cntfrq1[1]  ; regout           ;
; |series_detection|series:inst|cntfrq1[2]  ; |series_detection|series:inst|cntfrq1[2]  ; regout           ;
; |series_detection|series:inst|Equal1~141  ; |series_detection|series:inst|Equal1~141  ; combout          ;
; |series_detection|series:inst|cntfrq1[5]  ; |series_detection|series:inst|cntfrq1[5]  ; regout           ;
; |series_detection|series:inst|cntfrq1[7]  ; |series_detection|series:inst|cntfrq1[7]  ; regout           ;
; |series_detection|series:inst|cntfrq1[4]  ; |series_detection|series:inst|cntfrq1[4]  ; regout           ;
; |series_detection|series:inst|cntfrq1[6]  ; |series_detection|series:inst|cntfrq1[6]  ; regout           ;
; |series_detection|series:inst|Equal1~142  ; |series_detection|series:inst|Equal1~142  ; combout          ;
; |series_detection|series:inst|cntfrq1[8]  ; |series_detection|series:inst|cntfrq1[8]  ; regout           ;
; |series_detection|series:inst|Equal1~143  ; |series_detection|series:inst|Equal1~143  ; combout          ;
; |series_detection|series:inst|Add0~300    ; |series_detection|series:inst|Add0~300    ; combout          ;
; |series_detection|series:inst|Add0~300    ; |series_detection|series:inst|Add0~301    ; cout             ;
; |series_detection|series:inst|cntfrq0~231 ; |series_detection|series:inst|cntfrq0~231 ; combout          ;
; |series_detection|series:inst|Add0~302    ; |series_detection|series:inst|Add0~302    ; combout          ;
; |series_detection|series:inst|Add0~302    ; |series_detection|series:inst|Add0~303    ; cout             ;
; |series_detection|series:inst|Add0~304    ; |series_detection|series:inst|Add0~304    ; combout          ;
; |series_detection|series:inst|Add0~304    ; |series_detection|series:inst|Add0~305    ; cout             ;
; |series_detection|series:inst|Add0~306    ; |series_detection|series:inst|Add0~306    ; combout          ;
; |series_detection|series:inst|Add0~306    ; |series_detection|series:inst|Add0~307    ; cout             ;
; |series_detection|series:inst|Add0~308    ; |series_detection|series:inst|Add0~308    ; combout          ;
; |series_detection|series:inst|Add0~308    ; |series_detection|series:inst|Add0~309    ; cout             ;
; |series_detection|series:inst|Add0~310    ; |series_detection|series:inst|Add0~310    ; combout          ;
; |series_detection|series:inst|Add0~310    ; |series_detection|series:inst|Add0~311    ; cout             ;
; |series_detection|series:inst|Add0~312    ; |series_detection|series:inst|Add0~312    ; combout          ;
; |series_detection|series:inst|Add0~312    ; |series_detection|series:inst|Add0~313    ; cout             ;
; |series_detection|series:inst|cntfrq0~232 ; |series_detection|series:inst|cntfrq0~232 ; combout          ;
; |series_detection|series:inst|Add0~314    ; |series_detection|series:inst|Add0~314    ; combout          ;
; |series_detection|series:inst|Add0~314    ; |series_detection|series:inst|Add0~315    ; cout             ;
; |series_detection|series:inst|Add0~316    ; |series_detection|series:inst|Add0~316    ; combout          ;
; |series_detection|series:inst|Add0~316    ; |series_detection|series:inst|Add0~317    ; cout             ;
; |series_detection|series:inst|Add0~318    ; |series_detection|series:inst|Add0~318    ; combout          ;
; |series_detection|series:inst|Add0~318    ; |series_detection|series:inst|Add0~319    ; cout             ;
; |series_detection|series:inst|Add0~320    ; |series_detection|series:inst|Add0~320    ; combout          ;
; |series_detection|series:inst|Add1~180    ; |series_detection|series:inst|Add1~180    ; combout          ;
; |series_detection|series:inst|Add1~180    ; |series_detection|series:inst|Add1~181    ; cout             ;
; |series_detection|series:inst|Add1~182    ; |series_detection|series:inst|Add1~182    ; combout          ;
; |series_detection|series:inst|Add1~182    ; |series_detection|series:inst|Add1~183    ; cout             ;
; |series_detection|series:inst|Add1~184    ; |series_detection|series:inst|Add1~184    ; combout          ;
; |series_detection|series:inst|Add1~184    ; |series_detection|series:inst|Add1~185    ; cout             ;
; |series_detection|series:inst|Add1~186    ; |series_detection|series:inst|Add1~186    ; combout          ;
; |series_detection|series:inst|Add1~186    ; |series_detection|series:inst|Add1~187    ; cout             ;
; |series_detection|series:inst|cntfrq1~413 ; |series_detection|series:inst|cntfrq1~413 ; combout          ;
; |series_detection|series:inst|cntfrq1~414 ; |series_detection|series:inst|cntfrq1~414 ; combout          ;
; |series_detection|series:inst|Add1~188    ; |series_detection|series:inst|Add1~188    ; combout          ;
; |series_detection|series:inst|Add1~188    ; |series_detection|series:inst|Add1~189    ; cout             ;
; |series_detection|series:inst|Add1~190    ; |series_detection|series:inst|Add1~190    ; combout          ;
; |series_detection|series:inst|Add1~190    ; |series_detection|series:inst|Add1~191    ; cout             ;
; |series_detection|series:inst|cntfrq1~415 ; |series_detection|series:inst|cntfrq1~415 ; combout          ;
; |series_detection|series:inst|Add1~192    ; |series_detection|series:inst|Add1~192    ; combout          ;
; |series_detection|series:inst|Add1~192    ; |series_detection|series:inst|Add1~193    ; cout             ;
; |series_detection|series:inst|Add1~194    ; |series_detection|series:inst|Add1~194    ; combout          ;
; |series_detection|series:inst|Add1~194    ; |series_detection|series:inst|Add1~195    ; cout             ;
; |series_detection|series:inst|cntfrq1~416 ; |series_detection|series:inst|cntfrq1~416 ; combout          ;
; |series_detection|series:inst|Add1~196    ; |series_detection|series:inst|Add1~196    ; combout          ;
; |series_detection|series:inst|Add1~196    ; |series_detection|series:inst|Add1~197    ; cout             ;
; |series_detection|series:inst|cntfrq1~417 ; |series_detection|series:inst|cntfrq1~417 ; combout          ;
; |series_detection|series:inst|Add1~198    ; |series_detection|series:inst|Add1~198    ; combout          ;
; |series_detection|series:inst|Add1~198    ; |series_detection|series:inst|Add1~199    ; cout             ;
; |series_detection|series:inst|Add1~200    ; |series_detection|series:inst|Add1~200    ; combout          ;
; |series_detection|clk                     ; |series_detection|clk                     ; combout          ;
; |series_detection|clk~clkctrl             ; |series_detection|clk~clkctrl             ; outclk           ;
+-------------------------------------------+-------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                             ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; Node Name                                       ; Output Port Name                                ; Output Port Type ;
+-------------------------------------------------+-------------------------------------------------+------------------+
; |series_detection|state:inst1|z                 ; |series_detection|state:inst1|z                 ; regout           ;
; |series_detection|state:inst1|current_state[3]  ; |series_detection|state:inst1|current_state[3]  ; regout           ;
; |series_detection|state:inst1|current_state[2]  ; |series_detection|state:inst1|current_state[2]  ; regout           ;
; |series_detection|state:inst1|current_state[1]  ; |series_detection|state:inst1|current_state[1]  ; regout           ;
; |series_detection|state:inst1|current_state[5]  ; |series_detection|state:inst1|current_state[5]  ; regout           ;
; |series_detection|state:inst1|current_state[0]  ; |series_detection|state:inst1|current_state[0]  ; regout           ;
; |series_detection|state:inst1|current_state[4]  ; |series_detection|state:inst1|current_state[4]  ; regout           ;
; |series_detection|state:inst1|Mux1~667          ; |series_detection|state:inst1|Mux1~667          ; combout          ;
; |series_detection|state:inst1|Mux1~668          ; |series_detection|state:inst1|Mux1~668          ; combout          ;
; |series_detection|state:inst1|Mux1~669          ; |series_detection|state:inst1|Mux1~669          ; combout          ;
; |series_detection|state:inst1|Mux1~670          ; |series_detection|state:inst1|Mux1~670          ; combout          ;
; |series_detection|state:inst1|Mux1~671          ; |series_detection|state:inst1|Mux1~671          ; combout          ;
; |series_detection|state:inst1|Mux1~672          ; |series_detection|state:inst1|Mux1~672          ; combout          ;
; |series_detection|state:inst1|current_state[7]  ; |series_detection|state:inst1|current_state[7]  ; regout           ;
; |series_detection|state:inst1|current_state[6]  ; |series_detection|state:inst1|current_state[6]  ; regout           ;
; |series_detection|state:inst1|Mux1~673          ; |series_detection|state:inst1|Mux1~673          ; combout          ;
; |series_detection|state:inst1|Mux1~674          ; |series_detection|state:inst1|Mux1~674          ; combout          ;
; |series_detection|state:inst1|Mux1~675          ; |series_detection|state:inst1|Mux1~675          ; combout          ;
; |series_detection|series:inst|clk0              ; |series_detection|series:inst|clk0              ; regout           ;
; |series_detection|state:inst1|cnt[4]            ; |series_detection|state:inst1|cnt[4]            ; regout           ;
; |series_detection|state:inst1|cnt[0]            ; |series_detection|state:inst1|cnt[0]            ; regout           ;
; |series_detection|state:inst1|cnt[1]            ; |series_detection|state:inst1|cnt[1]            ; regout           ;
; |series_detection|state:inst1|cnt[2]            ; |series_detection|state:inst1|cnt[2]            ; regout           ;
; |series_detection|state:inst1|cnt[3]            ; |series_detection|state:inst1|cnt[3]            ; regout           ;
; |series_detection|state:inst1|Equal0~34         ; |series_detection|state:inst1|Equal0~34         ; combout          ;
; |series_detection|state:inst1|next_state[3]     ; |series_detection|state:inst1|next_state[3]     ; regout           ;
; |series_detection|series:inst|clk1              ; |series_detection|series:inst|clk1              ; regout           ;
; |series_detection|state:inst1|next_state[2]     ; |series_detection|state:inst1|next_state[2]     ; regout           ;
; |series_detection|state:inst1|next_state[1]     ; |series_detection|state:inst1|next_state[1]     ; regout           ;
; |series_detection|state:inst1|next_state[5]     ; |series_detection|state:inst1|next_state[5]     ; regout           ;
; |series_detection|state:inst1|next_state[0]     ; |series_detection|state:inst1|next_state[0]     ; regout           ;
; |series_detection|state:inst1|next_state[4]     ; |series_detection|state:inst1|next_state[4]     ; regout           ;
; |series_detection|state:inst1|next_state[7]     ; |series_detection|state:inst1|next_state[7]     ; regout           ;
; |series_detection|state:inst1|next_state[6]     ; |series_detection|state:inst1|next_state[6]     ; regout           ;
; |series_detection|series:inst|clkfrq0           ; |series_detection|series:inst|clkfrq0           ; regout           ;
; |series_detection|series:inst|cntfrq0[11]       ; |series_detection|series:inst|cntfrq0[11]       ; regout           ;
; |series_detection|series:inst|cntfrq0[10]       ; |series_detection|series:inst|cntfrq0[10]       ; regout           ;
; |series_detection|series:inst|Equal0~263        ; |series_detection|series:inst|Equal0~263        ; combout          ;
; |series_detection|series:inst|cntfrq0[12]       ; |series_detection|series:inst|cntfrq0[12]       ; regout           ;
; |series_detection|series:inst|cntfrq0[13]       ; |series_detection|series:inst|cntfrq0[13]       ; regout           ;
; |series_detection|series:inst|cntfrq0[14]       ; |series_detection|series:inst|cntfrq0[14]       ; regout           ;
; |series_detection|series:inst|cntfrq0[15]       ; |series_detection|series:inst|cntfrq0[15]       ; regout           ;
; |series_detection|series:inst|Equal0~264        ; |series_detection|series:inst|Equal0~264        ; combout          ;
; |series_detection|series:inst|Equal0~265        ; |series_detection|series:inst|Equal0~265        ; combout          ;
; |series_detection|series:inst|cntfrq0[16]       ; |series_detection|series:inst|cntfrq0[16]       ; regout           ;
; |series_detection|series:inst|cntfrq0[18]       ; |series_detection|series:inst|cntfrq0[18]       ; regout           ;
; |series_detection|series:inst|cntfrq0[19]       ; |series_detection|series:inst|cntfrq0[19]       ; regout           ;