series_detection.map.rpt

FPGA实验：用于检测输入的二进制系列

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                              ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                              ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------+
; series_detection.bdf             ; yes             ; User Block Diagram/Schematic File  ; E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf ;
; state.vhd                        ; yes             ; Other                              ; E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd            ;
; series.vhd                       ; yes             ; Other                              ; E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd           ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 119   ;
; Total combinational functions               ; 119   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 41    ;
;     -- 3 input functions                    ; 11    ;
;     -- <=2 input functions                  ; 67    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 78    ;
;     -- arithmetic mode                      ; 41    ;
; Total registers                             ; 83    ;
; I/O pins                                    ; 20    ;
; Maximum fan-out node                        ; rst   ;
; Maximum fan-out                             ; 70    ;
; Total fan-out                               ; 558   ;
; Average fan-out                             ; 2.51  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name           ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------+
; |series_detection          ; 119 (0)           ; 83 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 20   ; 0            ; |series_detection             ;
;    |series:inst|           ; 77 (77)           ; 61 (61)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |series_detection|series:inst ;
;    |state:inst1|           ; 42 (42)           ; 22 (22)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |series_detection|state:inst1 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 83    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 55    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 9     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |series_detection|state:inst1|Mux5         ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |series_detection|state:inst1|next_state~1 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+


+----------------------------------------+
; Source assignments for state:inst1     ;
+----------------+-------+------+--------+
; Assignment     ; Value ; From ; To     ;
+----------------+-------+------+--------+
; POWER_UP_LEVEL ; Low   ; -    ; cnt[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[4] ;
+----------------+-------+------+--------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Fri Oct 31 15:19:34 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off series_detection -c series_detection
Info: Found 1 design units, including 1 entities, in source file series_detection.bdf
    Info: Found entity 1: series_detection
Info: Elaborating entity "series_detection" for the top level hierarchy
Warning: Using design file state.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: state-state_switch
    Info: Found entity 1: state
Info: Elaborating entity "state" for hierarchy "state:inst1"
Warning: Using design file series.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: series-series_arch
    Info: Found entity 1: series
Info: Elaborating entity "series" for hierarchy "series:inst"
Info: Implemented 164 device resources after synthesis - the final resource count might be different
    Info: Implemented 19 input pins
    Info: Implemented 1 output pins
    Info: Implemented 144 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Oct 31 15:19:41 2008
    Info: Elapsed time: 00:00:08