mizi.vhd

设计一个符号显示电路

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mizi is
  port(seg:out std_logic_vector(16 downto 0);
       scan: out std_logic_vector(3 downto 0);
       clk:in std_logic);
end;

architecture one of mizi is
    signal cnt10	:	std_logic_vector(3 downto 0);
    --signal data		:	integer range 0 to 4;
    signal cnt16    :   std_logic_vector(3 downto 0);
    signal gw    :   std_logic_vector(1 downto 0);
    signal dw    :   std_logic_vector(1 downto 0);
type data1 is ('0','1','2','3','4','b','c','d','p','x','z','s');
signal data : data1;

begin 
------------------16进制计数器
process(clk)
begin
if (clk'event and clk='1') then
   if (cnt16="1111") then  
        cnt16<="0000";
   else
         cnt16<=cnt16+'1';
   end if;
end if;
end process;
------------------计数器分频
gw<=cnt16(3 downto 2);
dw<=cnt16(1 downto 0);

------------------数码管地址扫描
------------------第一行
process(gw,dw)
begin
if gw="00" then
  if dw="00" then  
       scan<="0111";data<='x';       --左
  elsif dw="01" then 
       scan<="1011";data<='b';
  elsif dw="10" then
       scan<="1101";data<='s';
  else 
       scan<="1110";data<='d';        --右
  end if;  
------------------第二行
elsif gw="01" then
  if dw="00" then  
       scan<="0111";data<='d';       --左
  elsif dw="01" then 
       scan<="1011";data<='z';
  elsif dw="10" then
       scan<="1101";data<='2';
  else 
       scan<="1110";data<='b';        --右
  end if;  
------------------第三行
elsif gw="10" then
  if dw="00" then  
       scan<="0111";data<='d';       --左
  elsif dw="01" then 
       scan<="1011";data<='p';
  elsif dw="10" then
       scan<="1101";data<='c';
  else 
       scan<="1110";data<='0';        --右
  end if;  
------------------第四行
elsif gw="11" then
  if dw="00" then  
       scan<="0111";data<='1';       --左
  elsif dw="01" then 
       scan<="1011";data<='2';
  elsif dw="10" then
       scan<="1101";data<='3';
  else 
       scan<="1110";data<='4';        --右
  end if;  
end if;
end process;
------------------17段译码
process(data)
begin
case data is    --dp p r n m k j h g f e d2 d1 c b a2 a1
   when '0'=>seg<="00000000011111111";
   when '1'=>seg<="00000000000001100";
   when '2'=>seg<="00001000101110111";
   when '3'=>seg<="00001000100111111";
   when '4'=>seg<="01001010110000000";
   when 'b'=>seg<="00010100111110011";
   when 'c'=>seg<="00000000011110011";
   when 'd'=>seg<="01000010000111111";
   when 'p'=>seg<="01001010000110110";
   when 's'=>seg<="00001000110111011";
   when 'x'=>seg<="00110101000000000";
   when 'z'=>seg<="00100100000110011";
   when others=>null;
end case;
end process;
end;