div2.vhd

来自「中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div2 is
port(clk:in std_logic;
	 clk2M:out std_logic;
	 clk4M:out std_logic);
end div2;

architecture one of div2 is
signal count:std_logic_vector(1 downto 0);
begin
	process(clk)
	begin
		if clk'event and clk='1'then
			count<=count+1;
		end if;
	end process;
	clk2M<=count(1);
	clk4M<=not count(0);
end one;