din5.map.qmsg

中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序列在时间上会错开一个采样间隔,需要进行定序处理,恢复成同步输出的I、Q 两路信号序列。现代雷达普遍采用相参信号处理,而如

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(18) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(18): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(19) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(19): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(20) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(20): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(21) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(21): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(22) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(22): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(23) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(23): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(24) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(24): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(25) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(25): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(26) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(26): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(27) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(27): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp Vhdl1.vhd(28) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(28): signal \"temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/Vhdl1.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "rom1.vhd 2 1 " "Warning: Using design file rom1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom1-SYN " "Info: Found design unit 1: rom1-SYN" {  } { { "rom1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/rom1.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom1 " "Info: Found entity 1: rom1" {  } { { "rom1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/rom1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom1 rom1:inst " "Info: Elaborating entity \"rom1\" for hierarchy \"rom1:inst\"" {  } { { "din5.bdf" "inst" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 200 360 576 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom1:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rom1:inst\|altsyncram:altsyncram_component\"" {  } { { "rom1.vhd" "altsyncram_component" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/rom1.vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rom1:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"rom1:inst\|altsyncram:altsyncram_component\"" {  } { { "rom1.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/rom1.vhd" 80 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fm51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fm51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fm51 " "Info: Found entity 1: altsyncram_fm51" {  } { { "db/altsyncram_fm51.tdf" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/db/altsyncram_fm51.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fm51 rom1:inst\|altsyncram:altsyncram_component\|altsyncram_fm51:auto_generated " "Info: Elaborating entity \"altsyncram_fm51\" for hierarchy \"rom1:inst\|altsyncram:altsyncram_component\|altsyncram_fm51:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "conter.vhd 2 1 " "Warning: Using design file conter.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 conter-SYN " "Info: Found design unit 1: conter-SYN" {  } { { "conter.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/conter.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 conter " "Info: Found entity 1: conter" {  } { { "conter.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/conter.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "conter conter:inst4 " "Info: Elaborating entity \"conter\" for hierarchy \"conter:inst4\"" {  } { { "din5.bdf" "inst4" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 192 88 232 256 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter conter:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"conter:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "conter.vhd" "lpm_counter_component" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/conter.vhd" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "conter:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"conter:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "conter.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/conter.vhd" 70 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_leh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_leh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_leh " "Info: Found entity 1: cntr_leh" {  } { { "db/cntr_leh.tdf" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/db/cntr_leh.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_leh conter:inst4\|lpm_counter:lpm_counter_component\|cntr_leh:auto_generated " "Info: Elaborating entity \"cntr_leh\" for hierarchy \"conter:inst4\|lpm_counter:lpm_counter_component\|cntr_leh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "237 " "Info: Implemented 237 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "39 " "Info: Implemented 39 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "185 " "Info: Implemented 185 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 05 16:31:49 2008 " "Info: Processing ended: Wed Nov 05 16:31:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}