din5.fnsim.qmsg

中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序列在时间上会错开一个采样间隔,需要进行定序处理,恢复成同步输出的I、Q 两路信号序列。现代雷达普遍采用相参信号处理,而如

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "move move:inst7 " "Info: Elaborating entity \"move\" for hierarchy \"move:inst7\"" {  } { { "din5.bdf" "inst7" { Schematic "E:/中频检波/din5/din5.bdf" { { 232 976 1120 424 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus60/libraries/others/maxplus2/74164.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus60/libraries/others/maxplus2/74164.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74164 " "Info: Found entity 1: 74164" {  } { { "74164.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74164.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74164 move:inst7\|74164:inst " "Info: Elaborating entity \"74164\" for hierarchy \"move:inst7\|74164:inst\"" {  } { { "move.bdf" "inst" { Schematic "E:/中频检波/din5/move.bdf" { { -80 152 272 96 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "move:inst7\|74164:inst " "Info: Elaborated megafunction instantiation \"move:inst7\|74164:inst\"" {  } { { "move.bdf" "" { Schematic "E:/中频检波/din5/move.bdf" { { -80 152 272 96 "inst" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xor_add xor_add:inst6 " "Info: Elaborating entity \"xor_add\" for hierarchy \"xor_add:inst6\"" {  } { { "din5.bdf" "inst6" { Schematic "E:/中频检波/din5/din5.bdf" { { 232 688 840 328 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(16) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(16): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 16 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(17) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(17): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(18) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(18): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(19) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(19): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(20) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(20): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(21) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(21): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(22) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(22): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(23) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(23): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(24) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(24): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(25) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(25): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(26) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(26): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din Vhdl1.vhd(27) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(27): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp Vhdl1.vhd(28) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(28): signal \"temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "rom.vhd 2 1 " "Warning: Using design file rom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom-SYN " "Info: Found design unit 1: rom-SYN" {  } { { "rom.vhd" "" { Text "E:/中频检波/din5/rom.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom " "Info: Found entity 1: rom" {  } { { "rom.vhd" "" { Text "E:/中频检波/din5/rom.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:inst3 " "Info: Elaborating entity \"rom\" for hierarchy \"rom:inst3\"" {  } { { "din5.bdf" "inst3" { Schematic "E:/中频检波/din5/din5.bdf" { { 200 360 576 336 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom:inst3\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rom:inst3\|altsyncram:altsyncram_component\"" {  } { { "rom.vhd" "altsyncram_component" { Text "E:/中频检波/din5/rom.vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}