din5.fnsim.qmsg

中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序列在时间上会错开一个采样间隔,需要进行定序处理,恢复成同步输出的I、Q 两路信号序列。现代雷达普遍采用相参信号处理,而如

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 02 15:02:33 2008 " "Info: Processing started: Sun Nov 02 15:02:33 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off din5 -c din5 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off din5 -c din5 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div5.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div5-one " "Info: Found design unit 1: div5-one" {  } { { "div5.vhd" "" { Text "E:/中频检波/din5/div5.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div5 " "Info: Found entity 1: div5" {  } { { "div5.vhd" "" { Text "E:/中频检波/din5/div5.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div2-one " "Info: Found design unit 1: div2-one" {  } { { "div2.vhd" "" { Text "E:/中频检波/din5/div2.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div2 " "Info: Found entity 1: div2" {  } { { "div2.vhd" "" { Text "E:/中频检波/din5/div2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "din5.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file din5.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 din5 " "Info: Found entity 1: din5" {  } { { "din5.bdf" "" { Schematic "E:/中频检波/din5/din5.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vhdl1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Vhdl1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 xor_add-one " "Info: Found design unit 1: xor_add-one" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 xor_add " "Info: Found entity 1: xor_add" {  } { { "Vhdl1.vhd" "" { Text "E:/中频检波/din5/Vhdl1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "move.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file move.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 move " "Info: Found entity 1: move" {  } { { "move.bdf" "" { Schematic "E:/中频检波/din5/move.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I5.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file I5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 I5-one " "Info: Found design unit 1: I5-one" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 I5 " "Info: Found entity 1: I5" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "din5 " "Info: Elaborating entity \"din5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div2 div2:inst10 " "Info: Elaborating entity \"div2\" for hierarchy \"div2:inst10\"" {  } { { "din5.bdf" "inst10" { Schematic "E:/中频检波/din5/din5.bdf" { { 96 360 456 192 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div5 div5:inst1 " "Info: Elaborating entity \"div5\" for hierarchy \"div5:inst1\"" {  } { { "din5.bdf" "inst1" { Schematic "E:/中频检波/din5/din5.bdf" { { 96 216 312 192 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I5 I5:inst8 " "Info: Elaborating entity \"I5\" for hierarchy \"I5:inst8\"" {  } { { "din5.bdf" "inst8" { Schematic "E:/中频检波/din5/din5.bdf" { { 376 72 208 504 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i4_temp I5.vhd(28) " "Warning (10492): VHDL Process Statement warning at I5.vhd(28): signal \"i4_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i6_temp I5.vhd(28) " "Warning (10492): VHDL Process Statement warning at I5.vhd(28): signal \"i6_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i4_6 I5.vhd(29) " "Warning (10492): VHDL Process Statement warning at I5.vhd(29): signal \"i4_6\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i4_6 I5.vhd(30) " "Warning (10492): VHDL Process Statement warning at I5.vhd(30): signal \"i4_6\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i4_6L I5.vhd(30) " "Warning (10492): VHDL Process Statement warning at I5.vhd(30): signal \"i4_6L\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i2_temp I5.vhd(31) " "Warning (10492): VHDL Process Statement warning at I5.vhd(31): signal \"i2_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i8_temp I5.vhd(31) " "Warning (10492): VHDL Process Statement warning at I5.vhd(31): signal \"i8_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i46 I5.vhd(32) " "Warning (10492): VHDL Process Statement warning at I5.vhd(32): signal \"i46\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "i2_8 I5.vhd(32) " "Warning (10492): VHDL Process Statement warning at I5.vhd(32): signal \"i2_8\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "I5.vhd" "" { Text "E:/中频检波/din5/I5.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}