din5.hier_info

中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序列在时间上会错开一个采样间隔,需要进行定序处理,恢复成同步输出的I、Q 两路信号序列。现代雷达普遍采用相参信号处理,而如

B => 2.IN1
QB <= 4.DB_MAX_OUTPUT_PORT_TYPE
QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
QD <= 6.DB_MAX_OUTPUT_PORT_TYPE
QE <= 7.DB_MAX_OUTPUT_PORT_TYPE
QF <= 8.DB_MAX_OUTPUT_PORT_TYPE
QG <= 9.DB_MAX_OUTPUT_PORT_TYPE
QH <= 10.DB_MAX_OUTPUT_PORT_TYPE


|din5|move:inst7|74164:inst5
QA <= 3.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 3.ACLR
CLRN => 4.ACLR
CLRN => 5.ACLR
CLRN => 6.ACLR
CLRN => 7.ACLR
CLRN => 8.ACLR
CLRN => 9.ACLR
CLRN => 10.ACLR
CLK => 3.CLK
CLK => 4.CLK
CLK => 5.CLK
CLK => 6.CLK
CLK => 7.CLK
CLK => 8.CLK
CLK => 9.CLK
CLK => 10.CLK
A => 2.IN0
B => 2.IN1
QB <= 4.DB_MAX_OUTPUT_PORT_TYPE
QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
QD <= 6.DB_MAX_OUTPUT_PORT_TYPE
QE <= 7.DB_MAX_OUTPUT_PORT_TYPE
QF <= 8.DB_MAX_OUTPUT_PORT_TYPE
QG <= 9.DB_MAX_OUTPUT_PORT_TYPE
QH <= 10.DB_MAX_OUTPUT_PORT_TYPE


|din5|move:inst7|74164:inst7
QA <= 3.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 3.ACLR
CLRN => 4.ACLR
CLRN => 5.ACLR
CLRN => 6.ACLR
CLRN => 7.ACLR
CLRN => 8.ACLR
CLRN => 9.ACLR
CLRN => 10.ACLR
CLK => 3.CLK
CLK => 4.CLK
CLK => 5.CLK
CLK => 6.CLK
CLK => 7.CLK
CLK => 8.CLK
CLK => 9.CLK
CLK => 10.CLK
A => 2.IN0
B => 2.IN1
QB <= 4.DB_MAX_OUTPUT_PORT_TYPE
QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
QD <= 6.DB_MAX_OUTPUT_PORT_TYPE
QE <= 7.DB_MAX_OUTPUT_PORT_TYPE
QF <= 8.DB_MAX_OUTPUT_PORT_TYPE
QG <= 9.DB_MAX_OUTPUT_PORT_TYPE
QH <= 10.DB_MAX_OUTPUT_PORT_TYPE


|din5|move:inst7|74164:inst11
QA <= 3.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 3.ACLR
CLRN => 4.ACLR
CLRN => 5.ACLR
CLRN => 6.ACLR
CLRN => 7.ACLR
CLRN => 8.ACLR
CLRN => 9.ACLR
CLRN => 10.ACLR
CLK => 3.CLK
CLK => 4.CLK
CLK => 5.CLK
CLK => 6.CLK
CLK => 7.CLK
CLK => 8.CLK
CLK => 9.CLK
CLK => 10.CLK
A => 2.IN0
B => 2.IN1
QB <= 4.DB_MAX_OUTPUT_PORT_TYPE
QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
QD <= 6.DB_MAX_OUTPUT_PORT_TYPE
QE <= 7.DB_MAX_OUTPUT_PORT_TYPE
QF <= 8.DB_MAX_OUTPUT_PORT_TYPE
QG <= 9.DB_MAX_OUTPUT_PORT_TYPE
QH <= 10.DB_MAX_OUTPUT_PORT_TYPE


|din5|move:inst7|74164:inst9
QA <= 3.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 3.ACLR
CLRN => 4.ACLR
CLRN => 5.ACLR
CLRN => 6.ACLR
CLRN => 7.ACLR
CLRN => 8.ACLR
CLRN => 9.ACLR
CLRN => 10.ACLR
CLK => 3.CLK
CLK => 4.CLK
CLK => 5.CLK
CLK => 6.CLK
CLK => 7.CLK
CLK => 8.CLK
CLK => 9.CLK
CLK => 10.CLK
A => 2.IN0
B => 2.IN1
QB <= 4.DB_MAX_OUTPUT_PORT_TYPE
QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
QD <= 6.DB_MAX_OUTPUT_PORT_TYPE
QE <= 7.DB_MAX_OUTPUT_PORT_TYPE
QF <= 8.DB_MAX_OUTPUT_PORT_TYPE
QG <= 9.DB_MAX_OUTPUT_PORT_TYPE
QH <= 10.DB_MAX_OUTPUT_PORT_TYPE


|din5|xor_add:inst6
clk => temp[0].IN0
clk => temp[1].IN0
clk => temp[2].IN0
clk => temp[3].IN0
clk => temp[4].IN0
clk => temp[5].IN0
clk => temp[6].IN0
clk => temp[7].IN0
clk => temp[8].IN0
clk => temp[9].IN0
clk => temp[10].IN0
clk => temp[11].IN0
clk => Add0.IN12
din[0] => temp[0].IN1
din[1] => temp[1].IN1
din[2] => temp[2].IN1
din[3] => temp[3].IN1
din[4] => temp[4].IN1
din[5] => temp[5].IN1
din[6] => temp[6].IN1
din[7] => temp[7].IN1
din[8] => temp[8].IN1
din[9] => temp[9].IN1
din[10] => temp[10].IN1
din[11] => temp[11].IN1
dout[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
dout[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|din5|rom1:inst
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]


|din5|rom1:inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_fm51:auto_generated.address_a[0]
address_a[1] => altsyncram_fm51:auto_generated.address_a[1]
address_a[2] => altsyncram_fm51:auto_generated.address_a[2]
address_a[3] => altsyncram_fm51:auto_generated.address_a[3]
address_a[4] => altsyncram_fm51:auto_generated.address_a[4]
address_a[5] => altsyncram_fm51:auto_generated.address_a[5]
address_a[6] => altsyncram_fm51:auto_generated.address_a[6]
address_a[7] => altsyncram_fm51:auto_generated.address_a[7]
address_a[8] => altsyncram_fm51:auto_generated.address_a[8]
address_a[9] => altsyncram_fm51:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_fm51:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_fm51:auto_generated.q_a[0]
q_a[1] <= altsyncram_fm51:auto_generated.q_a[1]
q_a[2] <= altsyncram_fm51:auto_generated.q_a[2]
q_a[3] <= altsyncram_fm51:auto_generated.q_a[3]
q_a[4] <= altsyncram_fm51:auto_generated.q_a[4]
q_a[5] <= altsyncram_fm51:auto_generated.q_a[5]
q_a[6] <= altsyncram_fm51:auto_generated.q_a[6]
q_a[7] <= altsyncram_fm51:auto_generated.q_a[7]
q_a[8] <= altsyncram_fm51:auto_generated.q_a[8]
q_a[9] <= altsyncram_fm51:auto_generated.q_a[9]
q_a[10] <= altsyncram_fm51:auto_generated.q_a[10]
q_a[11] <= altsyncram_fm51:auto_generated.q_a[11]
q_b[0] <= <GND>


|din5|rom1:inst|altsyncram:altsyncram_component|altsyncram_fm51:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT


|din5|conter:inst4
clock => lpm_counter:lpm_counter_component.clock
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]
q[8] <= lpm_counter:lpm_counter_component.q[8]
q[9] <= lpm_counter:lpm_counter_component.q[9]
q[10] <= lpm_counter:lpm_counter_component.q[10]
q[11] <= lpm_counter:lpm_counter_component.q[11]


|din5|conter:inst4|lpm_counter:lpm_counter_component
clock => cntr_leh:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_leh:auto_generated.q[0]
q[1] <= cntr_leh:auto_generated.q[1]
q[2] <= cntr_leh:auto_generated.q[2]
q[3] <= cntr_leh:auto_generated.q[3]
q[4] <= cntr_leh:auto_generated.q[4]
q[5] <= cntr_leh:auto_generated.q[5]
q[6] <= cntr_leh:auto_generated.q[6]
q[7] <= cntr_leh:auto_generated.q[7]
q[8] <= cntr_leh:auto_generated.q[8]
q[9] <= cntr_leh:auto_generated.q[9]
q[10] <= cntr_leh:auto_generated.q[10]
q[11] <= cntr_leh:auto_generated.q[11]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT