📄 din5.tan.qmsg

📁 中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序列在时间上会错开一个采样间隔,需要进行定序处理,恢复成同步输出的I、Q 两路信号序列。现代雷达普遍采用相参信号处理,而如
💻 QMSG
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{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "move:inst7\|74164:inst1\|7 inst5\[6\] clk 3.318 ns " "Info: Found hold time violation between source  pin or register \"move:inst7\|74164:inst1\|7\" and destination pin or register \"inst5\[6\]\" for clock \"clk\" (Hold time is 3.318 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.080 ns + Largest " "Info: + Largest clock skew is 4.080 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.384 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_16 8 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_16; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 120 0 168 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.486 ns) + CELL(0.827 ns) 2.612 ns div5:inst1\|clk_temp2 2 REG LC_X7_Y5_N2 2 " "Info: 2: + IC(0.486 ns) + CELL(0.827 ns) = 2.612 ns; Loc. = LC_X7_Y5_N2; Fanout = 2; REG Node = 'div5:inst1\|clk_temp2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk div5:inst1|clk_temp2 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(0.258 ns) 3.388 ns div5:inst1\|div5 3 COMB LC_X7_Y5_N5 151 " "Info: 3: + IC(0.518 ns) + CELL(0.258 ns) = 3.388 ns; Loc. = LC_X7_Y5_N5; Fanout = 151; COMB Node = 'div5:inst1\|div5'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.776 ns" { div5:inst1|clk_temp2 div5:inst1|div5 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.471 ns) + CELL(0.827 ns) 7.686 ns div2:inst10\|count\[0\] 4 REG LC_X8_Y6_N2 27 " "Info: 4: + IC(3.471 ns) + CELL(0.827 ns) = 7.686 ns; Loc. = LC_X8_Y6_N2; Fanout = 27; REG Node = 'div2:inst10\|count\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.298 ns" { div5:inst1|div5 div2:inst10|count[0] } "NODE_NAME" } } { "div2.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.069 ns) + CELL(0.629 ns) 11.384 ns inst5\[6\] 5 REG LC_X22_Y1_N4 1 " "Info: 5: + IC(3.069 ns) + CELL(0.629 ns) = 11.384 ns; Loc. = LC_X22_Y1_N4; Fanout = 1; REG Node = 'inst5\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.698 ns" { div2:inst10|count[0] inst5[6] } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 504 408 472 584 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.840 ns ( 33.73 % ) " "Info: Total cell delay = 3.840 ns ( 33.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.544 ns ( 66.27 % ) " "Info: Total interconnect delay = 7.544 ns ( 66.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.384 ns" { clk div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.384 ns" { clk clk~out0 div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[6] } { 0.000ns 0.000ns 0.486ns 0.518ns 3.471ns 3.069ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.304 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.304 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_16 8 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_16; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 120 0 168 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.486 ns) + CELL(0.827 ns) 2.612 ns div5:inst1\|clk_temp1 2 REG LC_X7_Y5_N1 2 " "Info: 2: + IC(0.486 ns) + CELL(0.827 ns) = 2.612 ns; Loc. = LC_X7_Y5_N1; Fanout = 2; REG Node = 'div5:inst1\|clk_temp1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk div5:inst1|clk_temp1 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.101 ns) 3.201 ns div5:inst1\|div5 3 COMB LC_X7_Y5_N5 151 " "Info: 3: + IC(0.488 ns) + CELL(0.101 ns) = 3.201 ns; Loc. = LC_X7_Y5_N5; Fanout = 151; COMB Node = 'div5:inst1\|div5'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.589 ns" { div5:inst1|clk_temp1 div5:inst1|div5 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.474 ns) + CELL(0.629 ns) 7.304 ns move:inst7\|74164:inst1\|7 4 REG LC_X22_Y1_N2 2 " "Info: 4: + IC(3.474 ns) + CELL(0.629 ns) = 7.304 ns; Loc. = LC_X22_Y1_N2; Fanout = 2; REG Node = 'move:inst7\|74164:inst1\|7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.103 ns" { div5:inst1|div5 move:inst7|74164:inst1|7 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74164.bdf" { { 536 360 424 616 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.856 ns ( 39.10 % ) " "Info: Total cell delay = 2.856 ns ( 39.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.448 ns ( 60.90 % ) " "Info: Total interconnect delay = 4.448 ns ( 60.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.304 ns" { clk div5:inst1|clk_temp1 div5:inst1|div5 move:inst7|74164:inst1|7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.304 ns" { clk clk~out0 div5:inst1|clk_temp1 div5:inst1|div5 move:inst7|74164:inst1|7 } { 0.000ns 0.000ns 0.486ns 0.488ns 3.474ns } { 0.000ns 1.299ns 0.827ns 0.101ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.384 ns" { clk div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.384 ns" { clk clk~out0 div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[6] } { 0.000ns 0.000ns 0.486ns 0.518ns 3.471ns 3.069ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.304 ns" { clk div5:inst1|clk_temp1 div5:inst1|div5 move:inst7|74164:inst1|7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.304 ns" { clk clk~out0 div5:inst1|clk_temp1 div5:inst1|div5 move:inst7|74164:inst1|7 } { 0.000ns 0.000ns 0.486ns 0.488ns 3.474ns } { 0.000ns 1.299ns 0.827ns 0.101ns 0.629ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns - " "Info: - Micro clock to output delay of source is 0.198 ns" {  } { { "74164.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74164.bdf" { { 536 360 424 616 "7" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.577 ns - Shortest register register " "Info: - Shortest register to register delay is 0.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns move:inst7\|74164:inst1\|7 1 REG LC_X22_Y1_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y1_N2; Fanout = 2; REG Node = 'move:inst7\|74164:inst1\|7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { move:inst7|74164:inst1|7 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74164.bdf" { { 536 360 424 616 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.475 ns) + CELL(0.102 ns) 0.577 ns inst5\[6\] 2 REG LC_X22_Y1_N4 1 " "Info: 2: + IC(0.475 ns) + CELL(0.102 ns) = 0.577 ns; Loc. = LC_X22_Y1_N4; Fanout = 1; REG Node = 'inst5\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.577 ns" { move:inst7|74164:inst1|7 inst5[6] } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 504 408 472 584 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.102 ns ( 17.68 % ) " "Info: Total cell delay = 0.102 ns ( 17.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.475 ns ( 82.32 % ) " "Info: Total interconnect delay = 0.475 ns ( 82.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.577 ns" { move:inst7|74164:inst1|7 inst5[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.577 ns" { move:inst7|74164:inst1|7 inst5[6] } { 0.000ns 0.475ns } { 0.000ns 0.102ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.013 ns + " "Info: + Micro hold delay of destination is 0.013 ns" {  } { { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 504 408 472 584 "inst5" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "74164.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74164.bdf" { { 536 360 424 616 "7" "" } } } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 504 408 472 584 "inst5" "" } } } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.384 ns" { clk div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.384 ns" { clk clk~out0 div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[6] } { 0.000ns 0.000ns 0.486ns 0.518ns 3.471ns 3.069ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.304 ns" { clk div5:inst1|clk_temp1 div5:inst1|div5 move:inst7|74164:inst1|7 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.304 ns" { clk clk~out0 div5:inst1|clk_temp1 div5:inst1|div5 move:inst7|74164:inst1|7 } { 0.000ns 0.000ns 0.486ns 0.488ns 3.474ns } { 0.000ns 1.299ns 0.827ns 0.101ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.577 ns" { move:inst7|74164:inst1|7 inst5[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.577 ns" { move:inst7|74164:inst1|7 inst5[6] } { 0.000ns 0.475ns } { 0.000ns 0.102ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Q_out\[0\] inst5\[0\] 15.986 ns register " "Info: tco from clock \"clk\" to destination pin \"Q_out\[0\]\" through register \"inst5\[0\]\" is 15.986 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.384 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_16 8 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_16; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 120 0 168 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.486 ns) + CELL(0.827 ns) 2.612 ns div5:inst1\|clk_temp2 2 REG LC_X7_Y5_N2 2 " "Info: 2: + IC(0.486 ns) + CELL(0.827 ns) = 2.612 ns; Loc. = LC_X7_Y5_N2; Fanout = 2; REG Node = 'div5:inst1\|clk_temp2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk div5:inst1|clk_temp2 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(0.258 ns) 3.388 ns div5:inst1\|div5 3 COMB LC_X7_Y5_N5 151 " "Info: 3: + IC(0.518 ns) + CELL(0.258 ns) = 3.388 ns; Loc. = LC_X7_Y5_N5; Fanout = 151; COMB Node = 'div5:inst1\|div5'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.776 ns" { div5:inst1|clk_temp2 div5:inst1|div5 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.471 ns) + CELL(0.827 ns) 7.686 ns div2:inst10\|count\[0\] 4 REG LC_X8_Y6_N2 27 " "Info: 4: + IC(3.471 ns) + CELL(0.827 ns) = 7.686 ns; Loc. = LC_X8_Y6_N2; Fanout = 27; REG Node = 'div2:inst10\|count\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.298 ns" { div5:inst1|div5 div2:inst10|count[0] } "NODE_NAME" } } { "div2.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.069 ns) + CELL(0.629 ns) 11.384 ns inst5\[0\] 5 REG LC_X20_Y4_N6 1 " "Info: 5: + IC(3.069 ns) + CELL(0.629 ns) = 11.384 ns; Loc. = LC_X20_Y4_N6; Fanout = 1; REG Node = 'inst5\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.698 ns" { div2:inst10|count[0] inst5[0] } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 504 408 472 584 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.840 ns ( 33.73 % ) " "Info: Total cell delay = 3.840 ns ( 33.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.544 ns ( 66.27 % ) " "Info: Total interconnect delay = 7.544 ns ( 66.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.384 ns" { clk div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.384 ns" { clk clk~out0 div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[0] } { 0.000ns 0.000ns 0.486ns 0.518ns 3.471ns 3.069ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 504 408 472 584 "inst5" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.404 ns + Longest register pin " "Info: + Longest register to pin delay is 4.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst5\[0\] 1 REG LC_X20_Y4_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y4_N6; Fanout = 1; REG Node = 'inst5\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inst5[0] } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 504 408 472 584 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.525 ns) + CELL(1.879 ns) 4.404 ns Q_out\[0\] 2 PIN PIN_28 0 " "Info: 2: + IC(2.525 ns) + CELL(1.879 ns) = 4.404 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'Q_out\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.404 ns" { inst5[0] Q_out[0] } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 520 536 712 536 "Q_out\[11..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.879 ns ( 42.67 % ) " "Info: Total cell delay = 1.879 ns ( 42.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.525 ns ( 57.33 % ) " "Info: Total interconnect delay = 2.525 ns ( 57.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.404 ns" { inst5[0] Q_out[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.404 ns" { inst5[0] Q_out[0] } { 0.000ns 2.525ns } { 0.000ns 1.879ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.384 ns" { clk div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.384 ns" { clk clk~out0 div5:inst1|clk_temp2 div5:inst1|div5 div2:inst10|count[0] inst5[0] } { 0.000ns 0.000ns 0.486ns 0.518ns 3.471ns 3.069ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.404 ns" { inst5[0] Q_out[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.404 ns" { inst5[0] Q_out[0] } { 0.000ns 2.525ns } { 0.000ns 1.879ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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