📄 din5.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 120 0 168 136 "clk" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div5:inst1\|clk_temp1 " "Info: Detected ripple clock \"div5:inst1\|clk_temp1\" as buffer" { } { { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div5:inst1\|clk_temp1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div5:inst1\|clk_temp2 " "Info: Detected ripple clock \"div5:inst1\|clk_temp2\" as buffer" { } { { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 14 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div5:inst1\|clk_temp2" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "div5:inst1\|div5 " "Info: Detected gated clock \"div5:inst1\|div5\" as buffer" { } { { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 7 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div5:inst1\|div5" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div2:inst10\|count\[0\] " "Info: Detected ripple clock \"div2:inst10\|count\[0\]\" as buffer" { } { { "div2.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div2.vhd" 16 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div2:inst10\|count\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register move:inst7\|74164:inst6\|6 register inst2\[11\] 136.43 MHz 7.33 ns Internal " "Info: Clock \"clk\" has Internal fmax of 136.43 MHz between source register \"move:inst7\|74164:inst6\|6\" and destination register \"inst2\[11\]\" (period= 7.33 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.140 ns + Longest register register " "Info: + Longest register to register delay is 7.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns move:inst7\|74164:inst6\|6 1 REG LC_X20_Y3_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y3_N5; Fanout = 4; REG Node = 'move:inst7\|74164:inst6\|6'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { move:inst7|74164:inst6|6 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74164.bdf" { { 416 360 424 496 "6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.509 ns) 1.644 ns I5:inst8\|Add0~237COUT1_247 2 COMB LC_X21_Y4_N7 2 " "Info: 2: + IC(1.135 ns) + CELL(0.509 ns) = 1.644 ns; Loc. = LC_X21_Y4_N7; Fanout = 2; COMB Node = 'I5:inst8\|Add0~237COUT1_247'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.644 ns" { move:inst7|74164:inst6|6 I5:inst8|Add0~237COUT1_247 } "NODE_NAME" } } { "d:/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.715 ns I5:inst8\|Add0~235COUT1_248 3 COMB LC_X21_Y4_N8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.715 ns; Loc. = LC_X21_Y4_N8; Fanout = 2; COMB Node = 'I5:inst8\|Add0~235COUT1_248'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { I5:inst8|Add0~237COUT1_247 I5:inst8|Add0~235COUT1_248 } "NODE_NAME" } } { "d:/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.228 ns) 1.943 ns I5:inst8\|Add0~233 4 COMB LC_X21_Y4_N9 6 " "Info: 4: + IC(0.000 ns) + CELL(0.228 ns) = 1.943 ns; Loc. = LC_X21_Y4_N9; Fanout = 6; COMB Node = 'I5:inst8\|Add0~233'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.228 ns" { I5:inst8|Add0~235COUT1_248 I5:inst8|Add0~233 } "NODE_NAME" } } { "d:/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.601 ns) 2.544 ns I5:inst8\|Add0~230 5 COMB LC_X21_Y3_N0 6 " "Info: 5: + IC(0.000 ns) + CELL(0.601 ns) = 2.544 ns; Loc. = LC_X21_Y3_N0; Fanout = 6; COMB Node = 'I5:inst8\|Add0~230'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.601 ns" { I5:inst8|Add0~233 I5:inst8|Add0~230 } "NODE_NAME" } } { "d:/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.061 ns) + CELL(0.382 ns) 3.987 ns I5:inst8\|i46\[6\]~51COUT1_61 6 COMB LC_X22_Y4_N7 2 " "Info: 6: + IC(1.061 ns) + CELL(0.382 ns) = 3.987 ns; Loc. = LC_X22_Y4_N7; Fanout = 2; COMB Node = 'I5:inst8\|i46\[6\]~51COUT1_61'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.443 ns" { I5:inst8|Add0~230 I5:inst8|i46[6]~51COUT1_61 } "NODE_NAME" } } { "I5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/I5.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.058 ns I5:inst8\|i46\[7\]~49COUT1_62 7 COMB LC_X22_Y4_N8 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.058 ns; Loc. = LC_X22_Y4_N8; Fanout = 2; COMB Node = 'I5:inst8\|i46\[7\]~49COUT1_62'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { I5:inst8|i46[6]~51COUT1_61 I5:inst8|i46[7]~49COUT1_62 } "NODE_NAME" } } { "I5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/I5.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.538 ns) 4.596 ns I5:inst8\|i46\[8\]~46 8 COMB LC_X22_Y4_N9 3 " "Info: 8: + IC(0.000 ns) + CELL(0.538 ns) = 4.596 ns; Loc. = LC_X22_Y4_N9; Fanout = 3; COMB Node = 'I5:inst8\|i46\[8\]~46'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.538 ns" { I5:inst8|i46[7]~49COUT1_62 I5:inst8|i46[8]~46 } "NODE_NAME" } } { "I5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/I5.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.374 ns) 6.034 ns inst2\[4\]~82 9 COMB LC_X23_Y3_N0 2 " "Info: 9: + IC(1.064 ns) + CELL(0.374 ns) = 6.034 ns; Loc. = LC_X23_Y3_N0; Fanout = 2; COMB Node = 'inst2\[4\]~82'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.438 ns" { I5:inst8|i46[8]~46 inst2[4]~82 } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.069 ns) 6.103 ns inst2\[5\]~81 10 COMB LC_X23_Y3_N1 2 " "Info: 10: + IC(0.000 ns) + CELL(0.069 ns) = 6.103 ns; Loc. = LC_X23_Y3_N1; Fanout = 2; COMB Node = 'inst2\[5\]~81'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.069 ns" { inst2[4]~82 inst2[5]~81 } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.069 ns) 6.172 ns inst2\[6\]~80 11 COMB LC_X23_Y3_N2 2 " "Info: 11: + IC(0.000 ns) + CELL(0.069 ns) = 6.172 ns; Loc. = LC_X23_Y3_N2; Fanout = 2; COMB Node = 'inst2\[6\]~80'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.069 ns" { inst2[5]~81 inst2[6]~80 } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.069 ns) 6.241 ns inst2\[7\]~79 12 COMB LC_X23_Y3_N3 2 " "Info: 12: + IC(0.000 ns) + CELL(0.069 ns) = 6.241 ns; Loc. = LC_X23_Y3_N3; Fanout = 2; COMB Node = 'inst2\[7\]~79'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.069 ns" { inst2[6]~80 inst2[7]~79 } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.157 ns) 6.398 ns inst2\[8\]~78 13 COMB LC_X23_Y3_N4 3 " "Info: 13: + IC(0.000 ns) + CELL(0.157 ns) = 6.398 ns; Loc. = LC_X23_Y3_N4; Fanout = 3; COMB Node = 'inst2\[8\]~78'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.157 ns" { inst2[7]~79 inst2[8]~78 } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.742 ns) 7.140 ns inst2\[11\] 14 REG LC_X23_Y3_N7 1 " "Info: 14: + IC(0.000 ns) + CELL(0.742 ns) = 7.140 ns; Loc. = LC_X23_Y3_N7; Fanout = 1; REG Node = 'inst2\[11\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.742 ns" { inst2[8]~78 inst2[11] } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.880 ns ( 54.34 % ) " "Info: Total cell delay = 3.880 ns ( 54.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.260 ns ( 45.66 % ) " "Info: Total interconnect delay = 3.260 ns ( 45.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.140 ns" { move:inst7|74164:inst6|6 I5:inst8|Add0~237COUT1_247 I5:inst8|Add0~235COUT1_248 I5:inst8|Add0~233 I5:inst8|Add0~230 I5:inst8|i46[6]~51COUT1_61 I5:inst8|i46[7]~49COUT1_62 I5:inst8|i46[8]~46 inst2[4]~82 inst2[5]~81 inst2[6]~80 inst2[7]~79 inst2[8]~78 inst2[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.140 ns" { move:inst7|74164:inst6|6 I5:inst8|Add0~237COUT1_247 I5:inst8|Add0~235COUT1_248 I5:inst8|Add0~233 I5:inst8|Add0~230 I5:inst8|i46[6]~51COUT1_61 I5:inst8|i46[7]~49COUT1_62 I5:inst8|i46[8]~46 inst2[4]~82 inst2[5]~81 inst2[6]~80 inst2[7]~79 inst2[8]~78 inst2[11] } { 0.000ns 1.135ns 0.000ns 0.000ns 0.000ns 1.061ns 0.000ns 0.000ns 1.064ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.509ns 0.071ns 0.228ns 0.601ns 0.382ns 0.071ns 0.538ns 0.374ns 0.069ns 0.069ns 0.069ns 0.157ns 0.742ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.706 ns - Smallest " "Info: - Smallest clock skew is 3.706 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.197 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 11.197 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_16 8 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_16; Fanout = 8; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 120 0 168 136 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.486 ns) + CELL(0.827 ns) 2.612 ns div5:inst1\|clk_temp1 2 REG LC_X7_Y5_N1 2 " "Info: 2: + IC(0.486 ns) + CELL(0.827 ns) = 2.612 ns; Loc. = LC_X7_Y5_N1; Fanout = 2; REG Node = 'div5:inst1\|clk_temp1'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk div5:inst1|clk_temp1 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.101 ns) 3.201 ns div5:inst1\|div5 3 COMB LC_X7_Y5_N5 151 " "Info: 3: + IC(0.488 ns) + CELL(0.101 ns) = 3.201 ns; Loc. = LC_X7_Y5_N5; Fanout = 151; COMB Node = 'div5:inst1\|div5'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.589 ns" { div5:inst1|clk_temp1 div5:inst1|div5 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.471 ns) + CELL(0.827 ns) 7.499 ns div2:inst10\|count\[0\] 4 REG LC_X8_Y6_N2 27 " "Info: 4: + IC(3.471 ns) + CELL(0.827 ns) = 7.499 ns; Loc. = LC_X8_Y6_N2; Fanout = 27; REG Node = 'div2:inst10\|count\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.298 ns" { div5:inst1|div5 div2:inst10|count[0] } "NODE_NAME" } } { "div2.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div2.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.069 ns) + CELL(0.629 ns) 11.197 ns inst2\[11\] 5 REG LC_X23_Y3_N7 1 " "Info: 5: + IC(3.069 ns) + CELL(0.629 ns) = 11.197 ns; Loc. = LC_X23_Y3_N7; Fanout = 1; REG Node = 'inst2\[11\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.698 ns" { div2:inst10|count[0] inst2[11] } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.683 ns ( 32.89 % ) " "Info: Total cell delay = 3.683 ns ( 32.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.514 ns ( 67.11 % ) " "Info: Total interconnect delay = 7.514 ns ( 67.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.197 ns" { clk div5:inst1|clk_temp1 div5:inst1|div5 div2:inst10|count[0] inst2[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.197 ns" { clk clk~out0 div5:inst1|clk_temp1 div5:inst1|div5 div2:inst10|count[0] inst2[11] } { 0.000ns 0.000ns 0.486ns 0.488ns 3.471ns 3.069ns } { 0.000ns 1.299ns 0.827ns 0.101ns 0.827ns 0.629ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.491 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.491 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_16 8 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_16; Fanout = 8; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 120 0 168 136 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.486 ns) + CELL(0.827 ns) 2.612 ns div5:inst1\|clk_temp2 2 REG LC_X7_Y5_N2 2 " "Info: 2: + IC(0.486 ns) + CELL(0.827 ns) = 2.612 ns; Loc. = LC_X7_Y5_N2; Fanout = 2; REG Node = 'div5:inst1\|clk_temp2'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk div5:inst1|clk_temp2 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(0.258 ns) 3.388 ns div5:inst1\|div5 3 COMB LC_X7_Y5_N5 151 " "Info: 3: + IC(0.518 ns) + CELL(0.258 ns) = 3.388 ns; Loc. = LC_X7_Y5_N5; Fanout = 151; COMB Node = 'div5:inst1\|div5'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.776 ns" { div5:inst1|clk_temp2 div5:inst1|div5 } "NODE_NAME" } } { "div5.vhd" "" { Text "C:/Documents and Settings/USER/桌面/中频检波/din5/div5.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.474 ns) + CELL(0.629 ns) 7.491 ns move:inst7\|74164:inst6\|6 4 REG LC_X20_Y3_N5 4 " "Info: 4: + IC(3.474 ns) + CELL(0.629 ns) = 7.491 ns; Loc. = LC_X20_Y3_N5; Fanout = 4; REG Node = 'move:inst7\|74164:inst6\|6'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.103 ns" { div5:inst1|div5 move:inst7|74164:inst6|6 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74164.bdf" { { 416 360 424 496 "6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.013 ns ( 40.22 % ) " "Info: Total cell delay = 3.013 ns ( 40.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.478 ns ( 59.78 % ) " "Info: Total interconnect delay = 4.478 ns ( 59.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.491 ns" { clk div5:inst1|clk_temp2 div5:inst1|div5 move:inst7|74164:inst6|6 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.491 ns" { clk clk~out0 div5:inst1|clk_temp2 div5:inst1|div5 move:inst7|74164:inst6|6 } { 0.000ns 0.000ns 0.486ns 0.518ns 3.474ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.629ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.197 ns" { clk div5:inst1|clk_temp1 div5:inst1|div5 div2:inst10|count[0] inst2[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.197 ns" { clk clk~out0 div5:inst1|clk_temp1 div5:inst1|div5 div2:inst10|count[0] inst2[11] } { 0.000ns 0.000ns 0.486ns 0.488ns 3.471ns 3.069ns } { 0.000ns 1.299ns 0.827ns 0.101ns 0.827ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.491 ns" { clk div5:inst1|clk_temp2 div5:inst1|div5 move:inst7|74164:inst6|6 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.491 ns" { clk clk~out0 div5:inst1|clk_temp2 div5:inst1|div5 move:inst7|74164:inst6|6 } { 0.000ns 0.000ns 0.486ns 0.518ns 3.474ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.629ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" { } { { "74164.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74164.bdf" { { 416 360 424 496 "6" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" { } { { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "74164.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/74164.bdf" { { 416 360 424 496 "6" "" } } } } { "din5.bdf" "" { Schematic "C:/Documents and Settings/USER/桌面/中频检波/din5/din5.bdf" { { 408 408 472 488 "inst2" "" } } } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.140 ns" { move:inst7|74164:inst6|6 I5:inst8|Add0~237COUT1_247 I5:inst8|Add0~235COUT1_248 I5:inst8|Add0~233 I5:inst8|Add0~230 I5:inst8|i46[6]~51COUT1_61 I5:inst8|i46[7]~49COUT1_62 I5:inst8|i46[8]~46 inst2[4]~82 inst2[5]~81 inst2[6]~80 inst2[7]~79 inst2[8]~78 inst2[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.140 ns" { move:inst7|74164:inst6|6 I5:inst8|Add0~237COUT1_247 I5:inst8|Add0~235COUT1_248 I5:inst8|Add0~233 I5:inst8|Add0~230 I5:inst8|i46[6]~51COUT1_61 I5:inst8|i46[7]~49COUT1_62 I5:inst8|i46[8]~46 inst2[4]~82 inst2[5]~81 inst2[6]~80 inst2[7]~79 inst2[8]~78 inst2[11] } { 0.000ns 1.135ns 0.000ns 0.000ns 0.000ns 1.061ns 0.000ns 0.000ns 1.064ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.509ns 0.071ns 0.228ns 0.601ns 0.382ns 0.071ns 0.538ns 0.374ns 0.069ns 0.069ns 0.069ns 0.157ns 0.742ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.197 ns" { clk div5:inst1|clk_temp1 div5:inst1|div5 div2:inst10|count[0] inst2[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.197 ns" { clk clk~out0 div5:inst1|clk_temp1 div5:inst1|div5 div2:inst10|count[0] inst2[11] } { 0.000ns 0.000ns 0.486ns 0.488ns 3.471ns 3.069ns } { 0.000ns 1.299ns 0.827ns 0.101ns 0.827ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.491 ns" { clk div5:inst1|clk_temp2 div5:inst1|div5 move:inst7|74164:inst6|6 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.491 ns" { clk clk~out0 div5:inst1|clk_temp2 div5:inst1|div5 move:inst7|74164:inst6|6 } { 0.000ns 0.000ns 0.486ns 0.518ns 3.474ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.629ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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