din5.flow.rpt

中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序列在时间上会错开一个采样间隔,需要进行定序处理,恢复成同步输出的I、Q 两路信号序列。现代雷达普遍采用相参信号处理,而如

Flow report for din5
Wed Nov 05 16:32:02 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+-------------------------+------------------------------------------+
; Flow Status             ; Successful - Wed Nov 05 16:32:02 2008    ;
; Quartus II Version      ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name           ; din5                                     ;
; Top-level Entity Name   ; din5                                     ;
; Family                  ; Cyclone                                  ;
; Device                  ; EP1C3T144C7                              ;
; Timing Models           ; Final                                    ;
; Met timing requirements ; No                                       ;
; Total logic elements    ; 185 / 2,910 ( 6 % )                      ;
; Total pins              ; 40 / 104 ( 38 % )                        ;
; Total virtual pins      ; 0                                        ;
; Total memory bits       ; 12,288 / 59,904 ( 21 % )                 ;
; Total PLLs              ; 0 / 1 ( 0 % )                            ;
+-------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 11/05/2008 16:31:45 ;
; Main task         ; Compilation         ;
; Revision Name     ; din5                ;
+-------------------+---------------------+


+--------------------------------------------------------------------+
; Flow Non-Default Global Settings                                   ;
+-----------------+-------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-----------------+-------+---------------+-------------+------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:05     ;
; Fitter               ; 00:00:04     ;
; Assembler            ; 00:00:01     ;
; Timing Analyzer      ; 00:00:01     ;
; Total                ; 00:00:11     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off din5 -c din5
quartus_fit --read_settings_files=off --write_settings_files=off din5 -c din5
quartus_asm --read_settings_files=off --write_settings_files=off din5 -c din5
quartus_tan --read_settings_files=off --write_settings_files=off din5 -c din5 --timing_analysis_only