div5.vhd

来自「中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序」· VHDL 代码 · 共 61 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div5 is
port(clk:in std_logic;
	 div5:out std_logic);
end div5;

architecture one of div5 is
signal cnt1:std_logic_vector(2 downto 0);
signal cnt2:std_logic_vector(2 downto 0);
signal clk_temp1:std_logic;
signal clk_temp2:std_logic;
constant m1:integer:=4;
constant m2:integer:=2;
begin
	process(clk)
	begin
	if clk'event and clk='1'then
		if cnt1=m1 then
			cnt1<="000";
			else cnt1<=cnt1+1;
		end if;
	end if;
	end process;
	
	process(clk)
	begin
		if clk'event and clk='1'then
			if cnt2=m1 then
				cnt2<="000";
			else
				cnt2<=cnt2+1;
			end if ;
		end if;
	end process;

	process(clk)
	begin
		if clk'event and clk='1'then
			if cnt1=0 then
				clk_temp1<='1';
			elsif cnt1=m2 then
				clk_temp1<='0';
			end if;
		end if;
	end process;

	process(clk)
	begin
		if clk'event and clk='0'then
			if cnt2=0 then
				clk_temp2<='1';
			elsif cnt2=m2 then
				clk_temp2<='0';
			end if;
		end if;
	end process;
div5<=clk_temp1 or clk_temp2;
end one;