din5.sim.rpt

来自「中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序」· RPT 代码 · 共 374 行 · 第 1/5 页

Simulator report for din5
Sun Nov 02 15:02:48 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|ALTSYNCRAM
  6. Coverage Summary
  7. Complete 1/0-Value Coverage
  8. Missing 1-Value Coverage
  9. Missing 0-Value Coverage
 10. Simulator INI Usage
 11. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 50.0 us      ;
; Simulation Netlist Size     ; 997 nodes    ;
; Simulation Coverage         ;      80.71 % ;
; Total Number of Transitions ; 143972       ;
; Simulation Breakpoints      ; 0            ;
; Family                      ; Cyclone      ;
+-----------------------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                                                  ;
+--------------------------------------------------------------------------------------------+----------------------------------------+---------------+
; Option                                                                                     ; Setting                                ; Default Value ;
+--------------------------------------------------------------------------------------------+----------------------------------------+---------------+
; Simulation mode                                                                            ; Functional                             ; Timing        ;
; Start time                                                                                 ; 0 ns                                   ; 0 ns          ;
; Vector input source                                                                        ; E:\Quartus6_project\din5\Waveform1.vwf ;               ;
; Add pins automatically to simulation output waveforms                                      ; On                                     ; On            ;
; Check outputs                                                                              ; Off                                    ; Off           ;
; Report simulation coverage                                                                 ; On                                     ; On            ;
; Display complete 1/0 value coverage report                                                 ; On                                     ; On            ;
; Display missing 1-value coverage report                                                    ; On                                     ; On            ;
; Display missing 0-value coverage report                                                    ; On                                     ; On            ;
; Detect setup and hold time violations                                                      ; Off                                    ; Off           ;
; Detect glitches                                                                            ; Off                                    ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off                                    ; Off           ;
; Generate Signal Activity File                                                              ; Off                                    ; Off           ;
; Group bus channels in simulation results                                                   ; Off                                    ; Off           ;