din5.map.rpt

中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序列在时间上会错开一个采样间隔,需要进行定序处理,恢复成同步输出的I、Q 两路信号序列。现代雷达普遍采用相参信号处理,而如

; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                       ;
; LPM_WIDTH              ; 12          ; Integer                                              ;
; LPM_DIRECTION          ; UP          ; Untyped                                              ;
; LPM_MODULUS            ; 0           ; Untyped                                              ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                              ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                              ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                              ;
; DEVICE_FAMILY          ; Cyclone     ; Untyped                                              ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                              ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                   ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                   ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                              ;
; LABWIDE_SCLR           ; ON          ; Untyped                                              ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                              ;
; CBXI_PARAMETER         ; cntr_leh    ; Untyped                                              ;
+------------------------+-------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Nov 05 16:31:44 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off din5 -c din5
Info: Found 2 design units, including 1 entities, in source file div5.vhd
    Info: Found design unit 1: div5-one
    Info: Found entity 1: div5
Info: Found 2 design units, including 1 entities, in source file div2.vhd
    Info: Found design unit 1: div2-one
    Info: Found entity 1: div2
Info: Found 1 design units, including 1 entities, in source file din5.bdf
    Info: Found entity 1: din5
Info: Found 2 design units, including 1 entities, in source file Vhdl1.vhd
    Info: Found design unit 1: xor_add-one
    Info: Found entity 1: xor_add
Info: Found 1 design units, including 1 entities, in source file move.bdf
    Info: Found entity 1: move
Info: Found 2 design units, including 1 entities, in source file I5.vhd
    Info: Found design unit 1: I5-one
    Info: Found entity 1: I5
Info: Elaborating entity "din5" for the top level hierarchy
Info: Elaborating entity "div2" for hierarchy "div2:inst10"
Info: Elaborating entity "div5" for hierarchy "div5:inst1"
Info: Elaborating entity "I5" for hierarchy "I5:inst8"
Warning (10492): VHDL Process Statement warning at I5.vhd(28): signal "i4_temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at I5.vhd(28): signal "i6_temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at I5.vhd(29): signal "i4_6" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at I5.vhd(30): signal "i4_6" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at I5.vhd(30): signal "i4_6L" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at I5.vhd(31): signal "i2_temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at I5.vhd(31): signal "i8_temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at I5.vhd(32): signal "i46" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at I5.vhd(32): signal "i2_8" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "move" for hierarchy "move:inst7"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/others/maxplus2/74164.bdf
    Info: Found entity 1: 74164
Info: Elaborating entity "74164" for hierarchy "move:inst7|74164:inst"
Info: Elaborated megafunction instantiation "move:inst7|74164:inst"
Info: Elaborating entity "xor_add" for hierarchy "xor_add:inst6"
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(16): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(17): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(18): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(19): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(20): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(21): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(22): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(23): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(24): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(25): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(26): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(27): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(28): signal "temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file rom1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: rom1-SYN
    Info: Found entity 1: rom1
Info: Elaborating entity "rom1" for hierarchy "rom1:inst"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "rom1:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "rom1:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fm51.tdf
    Info: Found entity 1: altsyncram_fm51
Info: Elaborating entity "altsyncram_fm51" for hierarchy "rom1:inst|altsyncram:altsyncram_component|altsyncram_fm51:auto_generated"
Warning: Using design file conter.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: conter-SYN
    Info: Found entity 1: conter
Info: Elaborating entity "conter" for hierarchy "conter:inst4"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "conter:inst4|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "conter:inst4|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_leh.tdf
    Info: Found entity 1: cntr_leh
Info: Elaborating entity "cntr_leh" for hierarchy "conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated"
Info: Implemented 237 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 39 output pins
    Info: Implemented 185 logic cells
    Info: Implemented 12 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Processing ended: Wed Nov 05 16:31:49 2008
    Info: Elapsed time: 00:00:05