i5.vhd

来自「中频验波是对信号进行中频直接采样和数字正交处理后,产生的I 支路和Q 支路信号序」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity I5 is
port(i2:in std_logic_vector(11 downto 0);
	 i4:in std_logic_vector(11 downto 0);
	 i6:in std_logic_vector(11 downto 0);
	 i8:in std_logic_vector(11 downto 0);
	 i5:out std_logic_vector(11 downto 0));
end I5;

architecture one of I5 is
signal i2_temp,i4_temp,i6_temp,i8_temp:std_logic_vector(15 downto 0);
signal i5_temp:std_logic_vector(15 downto 0);
signal i4_6:std_logic_vector(15 downto 0);
signal i4_6L:std_logic_vector(15 downto 0);
signal i46:std_logic_vector(15 downto 0);
signal i2_8:std_logic_vector(15 downto 0);

begin
	process(i2,i4,i6,i8)
	begin
		i2_temp<="0000"&i2;
		i4_temp<="0000"&i4;
		i6_temp<="0000"&i6;
		i8_temp<="0000"&i8;
		i4_6<=i4_temp+i6_temp;
		i4_6L<=i4_6(12 downto 0)&"000";
		i46<=i4_6+i4_6L;
		i2_8<=i2_temp+i8_temp;
		i5_temp<=i46-i2_8;
	end process;
i5<=i5_temp(15 downto 4);
end one;