din5.qsf

现代雷达普遍采用相参信号处理,而如何获得高精度基带数字正交( I , Q) 信号是整个系统信号处理成败的关键,以前通常的做法是采用模拟相位检波器得到I、Q信号,其正交性能一般为:幅度平衡在2 ％ 左右

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		din5_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T144C7
set_global_assignment -name TOP_LEVEL_ENTITY din5
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:43  OCTOBER 30, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VHDL_FILE div5.vhd
set_global_assignment -name VHDL_FILE div2.vhd
set_global_assignment -name BDF_FILE din5.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE din5.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name VECTOR_INPUT_SOURCE "E:\\Quartus6_project\\din5\\Waveform11.vwf"
set_global_assignment -name MIF_FILE "C:/Documents and Settings/Administrator/桌面/din5.mif"
set_global_assignment -name VHDL_FILE Vhdl1.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform2.vwf
set_global_assignment -name BDF_FILE move.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name VHDL_FILE I5.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform3.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform4.vwf
set_location_assignment PIN_16 -to clk
set_location_assignment PIN_59 -to clk4M
set_location_assignment PIN_37 -to clk8M
set_location_assignment PIN_71 -to I_out[11]
set_location_assignment PIN_70 -to I_out[10]
set_location_assignment PIN_69 -to I_out[9]
set_location_assignment PIN_68 -to I_out[8]
set_location_assignment PIN_67 -to I_out[7]
set_location_assignment PIN_62 -to I_out[6]
set_location_assignment PIN_61 -to I_out[5]
set_location_assignment PIN_60 -to I_out[4]
set_location_assignment PIN_79 -to Q_out[11]
set_location_assignment PIN_78 -to Q_out[10]
set_location_assignment PIN_77 -to Q_out[9]
set_location_assignment PIN_76 -to Q_out[8]
set_location_assignment PIN_75 -to Q_out[7]
set_location_assignment PIN_74 -to Q_out[6]
set_location_assignment PIN_73 -to Q_out[5]
set_location_assignment PIN_72 -to Q_out[4]
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPC2
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform11.vwf