din5.sim.rpt

现代雷达普遍采用相参信号处理,而如何获得高精度基带数字正交( I , Q) 信号是整个系统信号处理成败的关键,以前通常的做法是采用模拟相位检波器得到I、Q信号,其正交性能一般为:幅度平衡在2 ％ 左右

; |din5|Q_out[6]                                                                                      ; |din5|Q_out[6]                                                                                   ; pin_out          ;
; |din5|Q_out[5]                                                                                      ; |din5|Q_out[5]                                                                                   ; pin_out          ;
; |din5|Q_out[4]                                                                                      ; |din5|Q_out[4]                                                                                   ; pin_out          ;
; |din5|Q_out[3]                                                                                      ; |din5|Q_out[3]                                                                                   ; pin_out          ;
; |din5|Q_out[2]                                                                                      ; |din5|Q_out[2]                                                                                   ; pin_out          ;
; |din5|Q_out[1]                                                                                      ; |din5|Q_out[1]                                                                                   ; pin_out          ;
; |din5|Q_out[0]                                                                                      ; |din5|Q_out[0]                                                                                   ; pin_out          ;
; |din5|inst5[10]                                                                                     ; |din5|inst5[10]                                                                                  ; out              ;
; |din5|inst5[9]                                                                                      ; |din5|inst5[9]                                                                                   ; out              ;
; |din5|inst5[8]                                                                                      ; |din5|inst5[8]                                                                                   ; out              ;
; |din5|inst5[7]                                                                                      ; |din5|inst5[7]                                                                                   ; out              ;
; |din5|inst5[6]                                                                                      ; |din5|inst5[6]                                                                                   ; out              ;
; |din5|inst5[5]                                                                                      ; |din5|inst5[5]                                                                                   ; out              ;
; |din5|inst5[4]                                                                                      ; |din5|inst5[4]                                                                                   ; out              ;
; |din5|inst5[3]                                                                                      ; |din5|inst5[3]                                                                                   ; out              ;
; |din5|inst5[2]                                                                                      ; |din5|inst5[2]                                                                                   ; out              ;
; |din5|inst5[1]                                                                                      ; |din5|inst5[1]                                                                                   ; out              ;
; |din5|inst5[0]                                                                                      ; |din5|inst5[0]                                                                                   ; out              ;
; |din5|qp[11]                                                                                        ; |din5|qp[11]                                                                                     ; pin_out          ;
; |din5|qp[10]                                                                                        ; |din5|qp[10]                                                                                     ; pin_out          ;
; |din5|qp[9]                                                                                         ; |din5|qp[9]                                                                                      ; pin_out          ;
; |din5|qp[8]                                                                                         ; |din5|qp[8]                                                                                      ; pin_out          ;
; |din5|qp[7]                                                                                         ; |din5|qp[7]                                                                                      ; pin_out          ;
; |din5|qp[6]                                                                                         ; |din5|qp[6]                                                                                      ; pin_out          ;
; |din5|qp[5]                                                                                         ; |din5|qp[5]                                                                                      ; pin_out          ;
; |din5|qp[4]                                                                                         ; |din5|qp[4]                                                                                      ; pin_out          ;
; |din5|qp[3]                                                                                         ; |din5|qp[3]                                                                                      ; pin_out          ;
; |din5|qp[2]                                                                                         ; |din5|qp[2]                                                                                      ; pin_out          ;
; |din5|qp[1]                                                                                         ; |din5|qp[1]                                                                                      ; pin_out          ;
; |din5|qp[0]                                                                                         ; |din5|qp[0]                                                                                      ; pin_out          ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella0~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella0~COUT ; cout             ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella1~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella1~COUT ; cout             ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella2~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella2~COUT ; cout             ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella3~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella3~COUT ; cout             ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella4~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella4~COUT ; cout             ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella5~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella5~COUT ; cout             ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella6~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella6~COUT ; cout             ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella7~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella7~COUT ; cout             ;
; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella8~COMBOUT ; |din5|conter:inst4|lpm_counter:lpm_counter_component|cntr_leh:auto_generated|counter_cella8~COUT ; cout             ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[0]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[0]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[1]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[1]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[2]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[2]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[3]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[3]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[4]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[4]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[5]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[5]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[6]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[6]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[7]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[7]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[8]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[8]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[9]               ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[9]            ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[10]              ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[10]           ; portadataout0    ;
; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[11]              ; |din5|rom:inst3|altsyncram:altsyncram_component|altsyncram_vk61:auto_generated|q_a[11]           ; portadataout0    ;
; |din5|xor_add:inst6|temp[0]                                                                         ; |din5|xor_add:inst6|temp[0]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[1]                                                                         ; |din5|xor_add:inst6|temp[1]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[2]                                                                         ; |din5|xor_add:inst6|temp[2]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[3]                                                                         ; |din5|xor_add:inst6|temp[3]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[4]                                                                         ; |din5|xor_add:inst6|temp[4]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[5]                                                                         ; |din5|xor_add:inst6|temp[5]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[6]                                                                         ; |din5|xor_add:inst6|temp[6]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[7]                                                                         ; |din5|xor_add:inst6|temp[7]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[8]                                                                         ; |din5|xor_add:inst6|temp[8]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[9]                                                                         ; |din5|xor_add:inst6|temp[9]                                                                      ; out0             ;
; |din5|xor_add:inst6|temp[10]                                                                        ; |din5|xor_add:inst6|temp[10]                                                                     ; out0             ;
; |din5|xor_add:inst6|temp[11]                                                                        ; |din5|xor_add:inst6|temp[11]                                                                     ; out0             ;
; |din5|move:inst7|74164:inst9|3                                                                      ; |din5|move:inst7|74164:inst9|3                                                                   ; out              ;
; |din5|move:inst7|74164:inst9|4                                                                      ; |din5|move:inst7|74164:inst9|4                                                                   ; out              ;
; |din5|move:inst7|74164:inst9|5                                                                      ; |din5|move:inst7|74164:inst9|5                                                                   ; out              ;
; |din5|move:inst7|74164:inst9|6                                                                      ; |din5|move:inst7|74164:inst9|6                                                                   ; out              ;
; |din5|move:inst7|74164:inst9|7                                                                      ; |din5|move:inst7|74164:inst9|7                                                                   ; out              ;
; |din5|move:inst7|74164:inst9|8                                                                      ; |din5|move:inst7|74164:inst9|8                                                                   ; out              ;
; |din5|move:inst7|74164:inst9|9                                                                      ; |din5|move:inst7|74164:inst9|9                                                                   ; out              ;
; |din5|move:inst7|74164:inst9|10                                                                     ; |din5|move:inst7|74164:inst9|10                                                                  ; out              ;
; |din5|move:inst7|74164:inst7|3                                                                      ; |din5|move:inst7|74164:inst7|3                                                                   ; out              ;
; |din5|move:inst7|74164:inst7|4                                                                      ; |din5|move:inst7|74164:inst7|4                                                                   ; out              ;
; |din5|move:inst7|74164:inst7|5                                                                      ; |din5|move:inst7|74164:inst7|5                                                                   ; out              ;
; |din5|move:inst7|74164:inst7|6                                                                      ; |din5|move:inst7|74164:inst7|6                                                                   ; out              ;