📄 utx.v
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sUtx_State <=#UTX_DLY UTX_IDLE;
//Utx_Status_Table[{Utx_Cell_Fifo_Dout[15:13],Utx_Cell_Fifo_Dout[5:0]}] <=#UTX_DLY 1'b0;
Checked <=#UTX_DLY 1'b0;
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b0;
Check_Group_Buff <= #UTX_DLY Utx_Cell_Fifo_Dout[15:13];
end
//else
// sUtx_State <=#UTX_DLY UTX_CHECK; //<A NAME="等待一个时钟周期">
end
else
begin
sUtx_State <=#UTX_DLY UTX_IDLE;
Translate <=#UTX_DLY 1'b0;
Checked <=#UTX_DLY 1'b0;
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b0;
end
end
UTX_HEAD1: //<A NAME="发送信元头第1个16位字段">
begin
U2txdata <=#UTX_DLY Utx_Cell_Fifo_Dout[31:16]; //<A NAME="发送信元头第一个16位字段">
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b0;
Checked <=#UTX_DLY 1'b0;
if(U2txaddr!=8'hff) //<A NAME="地址与FF不同步">
begin
sUtx_State <=#UTX_DLY UTX_HEAD2;
U2txsoc <=#UTX_DLY 1'b1; //<A NAME="送SOC信号">
U2txenb <=#UTX_DLY U2txenb_Buffer; //<A NAME="送ENB信号">
Translate <=#UTX_DLY 1'b0; //<A NAME="端口选择结束">
Data_en_in <=#UTX_DLY 1'b1;
Init_in <=#UTX_DLY 1'b0;
end
else //<A NAME="地址与FF同步，等待一个时钟周期">
sUtx_State <=#UTX_DLY UTX_HEAD1;
end
UTX_HEAD2: //<A NAME="发送信元头第2个16位字段">
begin
sUtx_State <=#UTX_DLY UTX_HEC;
U2txdata <=#UTX_DLY Utx_Cell_Fifo_Dout[15:0]; //<A NAME="发送信元头第二个16位字段">
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b1;
U2txsoc <=#UTX_DLY 1'b0; //<A NAME="SOC清零">
Data_en_in <=#UTX_DLY 1'b0;
Init_in <=#UTX_DLY 1'b1;
end
UTX_HEC: //<A NAME="添加信元头HEC字段">
begin
sUtx_State <=#UTX_DLY UTX_PAYLOAD1;
U2txdata <=#UTX_DLY {Crc_Out,8'h00};
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b0;
end
UTX_PAYLOAD1://<A NAME="发送信元净荷DWARD高16位">
begin
U2txdata <=#UTX_DLY Utx_Cell_Fifo_Dout[31:16];
if(Utx_Payload_Cnt==4'b1011) //<A NAME="读信元结束">
begin
sUtx_State <=#UTX_DLY UTX_PAYLOAD2;
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b0;
end
else if(Utx_Payload_Cnt==4'b1100) //<A NAME="信元发送结束">
begin
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b0;
U2txenb <=#UTX_DLY 5'b11111;
// if(U2txaddr_Tx_Buffer!=U2txaddr_Buffer || Utx_Group_Cnt_Buffer!=U2group_Buff) //<A NAME="非当前轮询端口">
//begin
sUtx_State <=#UTX_DLY UTX_IDLE;
// Utx_Status_Table[{U2group_Buff,U2txaddr_Tx_Buffer[5:0]}] <=#UTX_DLY 1'b0; //<A NAME="清对应标志位">
U2txaddr_Tx_Buffer <=#UTX_DLY 8'hff;
//U2group_Buff <=#UTX_DLY 8'hff;
Check_Group_Buff <= #UTX_DLY 3'b111;
//end
//else
// sUtx_State <=UTX_PAYLOAD1 ; //<A NAME="等待当前端口轮询完毕">
end
else
begin
sUtx_State <=#UTX_DLY UTX_PAYLOAD2;
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b1;
end
end
UTX_PAYLOAD2: //<A NAME="发送信元净荷低16位">
begin
sUtx_State <=#UTX_DLY UTX_PAYLOAD1;
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b0;
U2txdata <=#UTX_DLY Utx_Cell_Fifo_Dout[15:0];
Utx_Payload_Cnt <=#UTX_DLY Utx_Payload_Cnt+4'b0001;
end
UTX_ULOOP_WAIT: //<A NAME="读ULOOP_FIFO等待">
begin
if(Uloop_Checked==1'b1) //<A NAME="检验信元描述字段通过">
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_HEAD1;
Uloop_Addr_Valid <=#UTX_DLY 1'b1;
Uloop_Fifo_Ren <=#UTX_DLY 1'b0;
end
else
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_CHECK;
Uloop_Fifo_Ren <=#UTX_DLY 1'b0;
end
end
UTX_ULOOP_CHECK: //<A NAME="uloop信元描述字段检验">
begin
if(Uloop_Fifo_Dout[32:31]==2'b11) //<A NAME="信元描述字段正确">
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_WAIT;
Uloop_Checked <=#UTX_DLY 1'b1;
Uloop_Fifo_Ren <=#UTX_DLY 1'b1;
Uloop_Addr_Valid <=#UTX_DLY 1'b1;
U2txaddr_Tx_Buffer <=#UTX_DLY Uloop_Fifo_Dout[7:0];
case(Uloop_Fifo_Dout[10:8])
3'b000:
U2txenb_Buffer <=5'b11110;
3'b001:
U2txenb_Buffer <=5'b11101;
3'b010:
U2txenb_Buffer <=5'b11011;
3'b011:
U2txenb_Buffer <=5'b10111;
3'b100:
U2txenb_Buffer <=5'b01111;
default:
U2txenb_Buffer <=5'b11110;
endcase
end
else
begin
sUtx_State <=#UTX_DLY UTX_IDLE;
Uloop_Checked <=#UTX_DLY 1'b0;
Uloop_Fifo_Ren <=#UTX_DLY 1'b0;
end
end
UTX_ULOOP_HEAD1: //<A NAME="发送A环回信元头DWARD高16位">
begin
U2txdata <=#UTX_DLY Uloop_Fifo_Dout[31:16]; //<A NAME="送出第一个信元头字段">
Uloop_Fifo_Ren <=#UTX_DLY 1'b0;
Uloop_Checked <=#UTX_DLY 1'b0;
if(U2txaddr!=8'hff)
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_HEAD2;
U2txsoc <=#UTX_DLY 1'b1;
Init_in <=#UTX_DLY 1'b0;
U2txenb <=#UTX_DLY U2txenb_Buffer;
Data_en_in <=#UTX_DLY 1'b1;
Uloop_Addr_Valid <=#UTX_DLY 1'b0;
end
else
sUtx_State <=#UTX_DLY UTX_ULOOP_HEAD1;
end
UTX_ULOOP_HEAD2: //<A NAME="发送A环回信元头DWARD低16位">
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_HEC;
U2txdata <=#UTX_DLY Uloop_Fifo_Dout[15:0];
Uloop_Fifo_Ren <=#UTX_DLY 1'b1;
U2txsoc <=#UTX_DLY 1'b0;
Data_en_in <=#UTX_DLY 1'b0;
Init_in <=#UTX_DLY 1'b1;
end
UTX_ULOOP_HEC: //<A NAME="添加HEC字段">
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_PAYLOAD1;
U2txdata <=#UTX_DLY {Crc_Out,8'h00};
Uloop_Fifo_Ren <=#UTX_DLY 1'b0;
end
UTX_ULOOP_PAYLOAD1: //<A NAME="发送A环回信元净荷高16位">
begin
U2txdata <=#UTX_DLY Uloop_Fifo_Dout[31:16];
if(Uloop_Payload_Cnt==4'b1011)
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_PAYLOAD2;
Uloop_Fifo_Ren <=#UTX_DLY 1'b0;
end
else if(Uloop_Payload_Cnt==4'b1100)
begin
sUtx_State <=#UTX_DLY UTX_IDLE;
Uloop_Fifo_Ren <=#UTX_DLY 1'b0;
U2txenb <=#UTX_DLY 5'b11111;
Uloop_Cnt_Add <=#UTX_DLY 1'b1;
end
else
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_PAYLOAD2;
Uloop_Fifo_Ren <=#UTX_DLY 1'b1;
end
end
UTX_ULOOP_PAYLOAD2: //<A NAME="发送A环回信元净荷低16位">
begin
sUtx_State <=#UTX_DLY UTX_ULOOP_PAYLOAD1;
Uloop_Payload_Cnt <=#UTX_DLY Uloop_Payload_Cnt+4'b0001;
U2txdata <=#UTX_DLY Uloop_Fifo_Dout[15:0];
Uloop_Fifo_Ren <=#UTX_DLY 1'b0;
end
UTX_MLOOP_WAIT: //<A NAME="MLOOP读FIFO等待">
begin
sUtx_State <=#UTX_DLY UTX_MLOOP_PAYLOAD;
Mloop_Fifo_Wen <=#UTX_DLY 1'b0;
Utx_Cell_Fifo_Ren <=#UTX_DLY 1'b0; //<A NAME="读信号清零">
end
UTX_MLOOP_PAYLOAD: //<A NAME="B环回写MLOOP_FIFO">
begin
sUtx_State <=#UTX_DLY UTX_IDLE;
if(Utx_Cell_Fifo_Dout[32:31]==2'b10)
Mloop_Fifo_Wen <=#UTX_DLY 1'b0;
else
begin
Mloop_Fifo_Din <=#UTX_DLY Utx_Cell_Fifo_Dout;
Mloop_Fifo_Wen <=#UTX_DLY 1'b1; //<A NAME="写入接收FIFO">
end
end
default:
sUtx_State <=#UTX_DLY UTX_IDLE;
endcase
end
end
always @ (posedge Rst or posedge Aclr_Utx or posedge Clk_UTP)
begin
if(Rst==1'b1)
Utx_Cell_Cnt <= 32'h00000000;
else if(Aclr_Utx==1'b1)
Utx_Cell_Cnt <= 32'h00000000;
else if(Utx_State_Buff==UTX_PAYLOAD1 && sUtx_State==UTX_IDLE)
Utx_Cell_Cnt <= #UTX_DLY Utx_Cell_Cnt + 32'h00000001;
else
Utx_Cell_Cnt <= #UTX_DLY Utx_Cell_Cnt;
end
always @ (posedge Rst or posedge Clk_UTP)
begin
if(Rst==1'b1 )
Uloop_Cell_Cnt <= 32'h00000000;
else if(Aclr_Uloop==1'b1)
Uloop_Cell_Cnt <= 32'h00000000;
else if(Uloop_Cnt_Add==1'b1)
Uloop_Cell_Cnt <= #UTX_DLY Uloop_Cell_Cnt + 32'h00000001;
else
Uloop_Cell_Cnt <= #UTX_DLY Uloop_Cell_Cnt;
end
always @ (posedge Rst or posedge Clk_UTP)
begin
if(Rst==1'b1)
begin
Uloop_Fifo_RdErr <= 1'b0;
Uloop_Fifo_WrErr <= 1'b0;
Mloop_Fifo_WrErr <= 1'b0;
Utx_Cell_Fifo_RdErr <= 1'b0;
Utx_Addr_Fifo_WrErr <= 1'b0;
end
else
begin
if(Uloop_Fifo_Empty==1'b1 && Uloop_Fifo_Ren==1'b1)
Uloop_Fifo_RdErr <= #UTX_DLY 1'b1;
else
Uloop_Fifo_RdErr <= #UTX_DLY Uloop_Fifo_RdErr;
if(Uloop_Fifo_Full==1'b1 && Uloop_Fifo_Wen==1'b1)
Uloop_Fifo_WrErr <= #UTX_DLY 1'b1;
else
Uloop_Fifo_WrErr <= #UTX_DLY Uloop_Fifo_WrErr;
if(Mloop_Fifo_Full==1'b1 && Mloop_Fifo_Wen==1'b1)
Mloop_Fifo_WrErr <= #UTX_DLY 1'b1;
else
Mloop_Fifo_WrErr <= #UTX_DLY Mloop_Fifo_WrErr;
if(Utx_Addr_Fifo_Full==1'b1 && Utx_Addr_Fifo_Wen==1'b1)
Utx_Addr_Fifo_WrErr <= #UTX_DLY 1'b1;
else
Utx_Addr_Fifo_WrErr <= #UTX_DLY Utx_Addr_Fifo_WrErr;
if(Utx_Cell_Fifo_Empty==1'b1 && Utx_Cell_Fifo_Ren==1'b1)
Utx_Cell_Fifo_RdErr <= #UTX_DLY 1'b1;
else
Utx_Cell_Fifo_RdErr <= #UTX_DLY Utx_Cell_Fifo_RdErr;
end
end
always @ (posedge Rst or posedge Clk_Sys)
begin
if(Rst==1'b1)
begin
Mloop_Fifo_RdErr <= 1'b0;
Utx_Addr_Fifo_RdErr <= 1'b0;
Utx_Cell_Fifo_WrErr <= 1'b0;
end
else
begin
if(Mloop_Fifo_Empty==1'b1 && Mloop_Fifo_Ren==1'b1)
Mloop_Fifo_RdErr <=#UTX_DLY 1'b1;
else
Mloop_Fifo_RdErr <=#UTX_DLY Mloop_Fifo_RdErr;
if(Utx_Addr_Fifo_Empty==1'b1 && Utx_Addr_Fifo_Ren==1'b1)
Utx_Addr_Fifo_RdErr <=#UTX_DLY 1'b1;
else
Utx_Addr_Fifo_RdErr <=#UTX_DLY Utx_Addr_Fifo_RdErr;
if(Utx_Cell_Fifo_Empty==1'b1 && Utx_Cell_Fifo_Ren==1'b1)
Utx_Cell_Fifo_WrErr <=#UTX_DLY 1'b1;
else
Utx_Cell_Fifo_WrErr <=#UTX_DLY Utx_Cell_Fifo_RdErr;
end
end
assign Utx_Test_Reg = {6'h00,sUtx_Poll,3'h0,sUtx_State,Uloop_Fifo_RdErr,Uloop_Fifo_WrErr,Uloop_Fifo_Empty,Uloop_Fifo_Full,Mloop_Fifo_RdErr,Mloop_Fifo_WrErr,Mloop_Fifo_Empty,Mloop_Fifo_Full,Utx_Addr_Fifo_RdErr,Utx_Addr_Fifo_WrErr,Utx_Cell_Fifo_Empty,Utx_Addr_Fifo_Full,Utx_Cell_Fifo_RdErr,Utx_Cell_Fifo_WrErr,Utx_Cell_Fifo_Empty,Utx_Cell_Fifo_Full};
endmodule
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