kernelboot1.s

嵌入式实时操作系统内核

;Kernel Boot File:
;Copyright (c) 2008 www.evvei.com, All Rights Reserved.
;______________________________________________________________________________________
;File Name: KernelBoot1.asm
;Abstract:  This file is the "asm" example source code for samsung s3c44b0x processor
;           for boot to the e-kernel.
;

    IMPORT	|Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
    IMPORT	|Image$$RW$$Base|   ; Base of RAM to initialise
    IMPORT	|Image$$ZI$$Base|   ; Base and limit of area
    IMPORT	|Image$$ZI$$Limit|  ; to zero initialise
    
    IMPORT   KernelBootContinue
    
;______________________________________________________________________________________
;Register address definitions.
;Interrupt Control:
INTCON      EQU  0x01e00000
INTPND	    EQU	 0x01e00004
INTMOD	    EQU	 0x01e00008
INTMSK	    EQU	 0x01e0000c
I_ISPR	    EQU	 0x01e00020
I_CMST	    EQU	 0x01e0001c

;Watchdog timer:
WTCON	    EQU	0x01d30000

;Clock Controller:
PLLCON	    EQU	 0x01d80000
CLKCON	    EQU	 0x01d80004
LOCKTIME    EQU	 0x01d8000c
	
;Memory Controller:
REFRESH	    EQU  0x01c80024
BWSCON      EQU  0x01c80000


;Tick timer control register.
TICNT    EQU   0x01d7008c

M_DIV	EQU	0x24
P_DIV	EQU	0x2
S_DIV	EQU	0x1	

;Temporary stack pointer for boot stage.
TempStack        equ   0x00010000

    
;______________________________________________________________________________________
;Code Section:

    AREA  KernelBootSection, CODE, READONLY
    
ImageCodeStart  
    B       KernelBoot
    
    SPACE   64
    

;Kernel boot start:
KernelBoot
    
    ;Disable watch dog timer first.
    ldr	    r0,=WTCON
    mov	    r1,#0		
    str	    r1,[r0]
    
    ;Mask all hardware interrupt source but unmask the global mask bit.
    ldr	    r0,=INTMSK
    ldr	    r1,=0x03ffffff
    str	    r1,[r0]
    
    ;Set the processor as non-vectored interrupt mode.
    LDR     r1,=INTCON
    MOV     r0,#5
    STR     r0,[r1]
    
    ;Set clock control registers.
    ldr     r0,=LOCKTIME
    ldr     r1,=0xfff
    str     r1,[r0]
    
    ;Set the PLL.Fin=10MHz,Fout=40MHz.
    ldr     r0,=PLLCON
    ldr     r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV)	
    str     r1,[r0]
    
    ;Enable all hardware units clock.
    ldr	    r0,=CLKCON		 
    ldr	    r1,=0x7ff8
    str	    r1,[r0]
    
    ;Set memory control registers.
    ldr	    r0,=SMRDATA
    ldmia   r0,{r1-r13}
    ldr	    r0,=BWSCON
    stmia   r0,{r1-r13}
    
    ;Initialize the hardware tick timer.(to 32Hz)
    ldr     r1,=TICNT
    mov     r0,#0x83
    strb    r0,[r1]
    
    
    ;Copy and paste RW data/zero initialized data.
    LDR	    r0, =|Image$$RO$$Limit|
    LDR	    r1, =|Image$$RW$$Base|
    LDR	    r3, =|Image$$ZI$$Base|	
	
    CMP	    r0, r1	       ;Check that they are different
    BEQ	    %F1
0		
    CMP	    r1, r3	       ;Copy init data
    LDRCC   r2, [r0], #4
    STRCC   r2, [r1], #4
    BCC	    %B0
1		
    LDR	    r1, =|Image$$ZI$$Limit|  ;Top of zero init segment
    MOV	    r2, #0
2		
    CMP	    r3, r1	       ;Zero init
    STRCC   r2, [r3], #4
    BCC	    %B2
    
    ;Set up the stack pointer for temporary using.
    ;Not that, user may not setup this pointer, if it is not required in boot stage.
    ldr	    sp, =TempStack
    
    
    ;Turn-on the processor cache.
    
    
    ;Jump to the "c" level boot function for continue kernel booting.
	B	KernelBootContinue
	
	
SMRDATA DATA
    DCD 0x22222220   ;Bank0=OM[1:0], Bank1~Bank7=32bit
    DCD 0x00000000   ;GCS0
    DCD 0x00000000   ;GCS1 
    DCD 0x00000000   ;GCS2
    DCD 0x00000000   ;GCS3
    DCD 0x00000000   ;GCS4
    DCD 0x00000000   ;GCS5
    DCD 0x00000000   ;GCS6
    DCD 0x00000000   ;GCS7
    DCD 0x00000000   ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
    DCD 0x00000010   ;SCLK power down mode, BANKSIZE 32M/32M
    DCD 0x00000020   ;MRSR6 CL=2clk
    DCD 0x00000020   ;MRSR7
	
	
    END