img_idct_8x8_12q4_c.c

dm642函数库

            /*  Stage 4 of signal flow graph.                               */
            /* ------------------------------------------------------------ */
            f0 = (g0 + h2);         f7 = (g0 - h2);
            f1 = (g1 + h3);         f6 = (g1 - h3);
            f2 = (h1 + g3);         f5 = (h1 - g3);
            f3 = (h0 + g2);         f4 = (h0 - g2);

            /* ------------------------------------------------------------ */
            /*  Stage 5:  Write sample-domain results.                      */
            /* ------------------------------------------------------------ */
            idct[i][0][j] = f0;
            idct[i][1][j] = f1;
            idct[i][2][j] = f2;
            idct[i][3][j] = f3;
            idct[i][4][j] = f4;
            idct[i][5][j] = f5;
            idct[i][6][j] = f6;
            idct[i][7][j] = f7;
        }
    }

    /* -------------------------------------------------------------------- */
    /*  Horizontal Pass                                                     */
    /*                                                                      */
    /*  This performs one IDCT per iteration on the 11Q5 results from       */
    /*  the previous pass.  Both horizontal and vertical passes are         */
    /*  scaled down by sqrt(2) -- the net effect of which is that the       */
    /*  IDCT results generated by this pass (prior to saturation) are       */
    /*  also 11Q5 results, only with no sqrt(2) factors remaining.          */
    /*                                                                      */
    /*  The IDCT butterflies in this pass are identical to the ones in      */
    /*  the vertical pass, except for an additional rounding value          */
    /*  which is added into the DC term early in the flow graph.            */
    /*                                                                      */
    /*  The 11Q5 sample-domain terms are saturated to 9Q7 values, and       */
    /*  then truncated to 9Q0 results before storing.                       */
    /*                                                                      */
    /*  The outer loop steps between IDCT blocks, whereas the inner         */
    /*  loop focuses on rows within each IDCT block.                        */
    /* -------------------------------------------------------------------- */
    for (i = 0; i < num_idcts; i++)
    {
        for (j = 0; j < 8; j++)
        {
            /* ------------------------------------------------------------ */
            /*  Stage 0:  Load in frequency-domain coefficients.            */
            /* ------------------------------------------------------------ */
            F0 = idct[i][j][0];
            F1 = idct[i][j][1];
            F2 = idct[i][j][2];
            F3 = idct[i][j][3];
            F4 = idct[i][j][4];
            F5 = idct[i][j][5];
            F6 = idct[i][j][6];
            F7 = idct[i][j][7];

            /* ------------------------------------------------------------ */
            /*  Stage 1 of signal flow graph.                               */
            /* ------------------------------------------------------------ */
            P0 = F0;                P1 = F4;
            R1 = F2;                R0 = F6;

            Q1 = (F1*C7 - F7*C1 + 0x8000) >> 16;
            Q0 = (F5*C3 - F3*C5 + 0x8000) >> 16;
            S0 = (F5*C5 + F3*C3 + 0x8000) >> 16;
            S1 = (F1*C1 + F7*C7 + 0x8000) >> 16;

            /* ------------------------------------------------------------ */
            /*  Stage 2 of signal flow graph.                               */
            /* ------------------------------------------------------------ */
            p0 = (((int)P0 + (int)P1 + 1) >> 1) + 15;
            p1 = (((int)P0 - (int)P1    ) >> 1) + 16;
            r1 = (R1*C6 - R0*C2 + 0x8000) >> 16;
            r0 = (R1*C2 + R0*C6 + 0x8000) >> 16;

            s1 = (S1 + S0);         q1 = (Q1 + Q0);
            s0 = (S1 - S0);         q0 = (Q1 - Q0);

            /* ------------------------------------------------------------ */
            /*  Stage 3 of signal flow graph.                               */
            /* ------------------------------------------------------------ */
            g0 = (p0 + r0);         g1 = (p1 + r1);
            h0 = (p0 - r0);         h1 = (p1 - r1);

            h2 = s1;                g2 = q1;
            g3 = (s0*C0 - q0*C0 + 0x8000) >> 16;
            h3 = (s0*C0 + q0*C0 + 0x8000) >> 16;

            /* ------------------------------------------------------------ */
            /*  Stage 4 of signal flow graph.                               */
            /* ------------------------------------------------------------ */
            f0 = (g0 + h2);         f7 = (g0 - h2);
            f1 = (g1 + h3);         f6 = (g1 - h3);
            f2 = (h1 + g3);         f5 = (h1 - g3);
            f3 = (h0 + g2);         f4 = (h0 - g2);

            /* ------------------------------------------------------------ */
            /*  Stage 4.1:  Q-pt adjust: Bit 15 is a don't-care.            */
            /* ------------------------------------------------------------ */
            f0r = f0 + f0;          f7r = f7 + f7;
            f1r = f1 + f1;          f6r = f6 + f6;
            f2r = f2 + f2;          f5r = f5 + f5;
            f3r = f3 + f3;          f4r = f4 + f4;

            /* ------------------------------------------------------------ */
            /*  Stage 4.2:  Saturate results to 9Q6.                        */
            /* ------------------------------------------------------------ */
            f0s = f0r > 0x3FFF ? 0x3FFF : f0r < -0x4000 ? -0x4000 : f0r;
            f1s = f1r > 0x3FFF ? 0x3FFF : f1r < -0x4000 ? -0x4000 : f1r;
            f2s = f2r > 0x3FFF ? 0x3FFF : f2r < -0x4000 ? -0x4000 : f2r;
            f3s = f3r > 0x3FFF ? 0x3FFF : f3r < -0x4000 ? -0x4000 : f3r;
            f4s = f4r > 0x3FFF ? 0x3FFF : f4r < -0x4000 ? -0x4000 : f4r;
            f5s = f5r > 0x3FFF ? 0x3FFF : f5r < -0x4000 ? -0x4000 : f5r;
            f6s = f6r > 0x3FFF ? 0x3FFF : f6r < -0x4000 ? -0x4000 : f6r;
            f7s = f7r > 0x3FFF ? 0x3FFF : f7r < -0x4000 ? -0x4000 : f7r;

            /* ------------------------------------------------------------ */
            /*  Stage 4.3:  Truncate results to 9Q0.                        */
            /* ------------------------------------------------------------ */
            f0t = f0s >> 6;         f7t = f7s >> 6;
            f1t = f1s >> 6;         f6t = f6s >> 6;
            f2t = f2s >> 6;         f5t = f5s >> 6;
            f3t = f3s >> 6;         f4t = f4s >> 6;

            /* ------------------------------------------------------------ */
            /*  Stage 5:  Store sample-domain results.                      */
            /* ------------------------------------------------------------ */
            idct[i][j][0] = f0t;
            idct[i][j][1] = f1t;
            idct[i][j][2] = f2t;
            idct[i][j][3] = f3t;
            idct[i][j][4] = f4t;
            idct[i][j][5] = f5t;
            idct[i][j][6] = f6t;
            idct[i][j][7] = f7t;
        }
    }

    return;
}

/* ======================================================================== */
/*  End of file:  img_idct_8x8_12q4.c                                       */
/* ------------------------------------------------------------------------ */
/*            Copyright (c) 2002 Texas Instruments, Incorporated.           */
/*                           All Rights Reserved.                           */
/* ======================================================================== */