pxa27x_registers.h

tinyos2.0版本驱动

#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
#define LSR_BI		(1 << 4)	/* Break Interrupt */
#define LSR_FE		(1 << 3)	/* Framing Error */
#define LSR_PE		(1 << 2)	/* Parity Error */
#define LSR_OE		(1 << 1)	/* Overrun Error */
#define LSR_DR		(1 << 0)	/* Data Ready */

#define MCR_AFE		(1 << 5)	/* Auto-Flow Control Enable */
#define MCR_LOOP	(1 << 4)	/* Loopback Mode */
#define MCR_OUT2	(1 << 3)	/* OUT2 Signal control */
#define MCR_OUT1	(1 << 2)	/* Test Bit */
#define MCR_RTS		(1 << 1)	/* Request to Send */
#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */

#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
#define MSR_RI		(1 << 6)	/* Ring Indicator */
#define MSR_DSR		(1 << 5)	/* Data Set Ready */
#define MSR_CTS		(1 << 4)	/* Clear To Send */
#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */

#define ISR_RXPL	(1 << 4)	/* Receive Data Polarity */
#define ISR_TXPL	(1 << 3)	/* Transmit Data Polarity */
#define ISR_XMODE	(1 << 2)	/* Transmit Pulse Width Select */
#define ISR_RCVEIR	(1 << 1)	/* Receiver SIR Enable */
#define ISR_XMITIR	(1 << 0)	/* Transmitter SIR Enable */


/******************************************************************************/
/* Standard I2C */
/******************************************************************************/
#define IBMR	_PXAREG(0x40301680) /* I2C Bus Monitor register 9-30 */
#define IDBR	_PXAREG(0x40301688) /* I2C Data Buffer register 9-29 */
#define ICR	_PXAREG(0x40301690) /* I2C Control register 9-23 */
#define ISR	_PXAREG(0x40301698) /* I2C Status register 9-26 */
#define ISAR	_PXAREG(0x403016A0) /* I2C Slave Address register 9-28 */

/* I2C - Control Register */
#define ICR_FM	        (1 << 15)	/* Fast Mode */
#define ICR_UR	        (1 << 14)	/* Unit Reset */
#define ICR_SADIE       (1 << 13)	/* Slave Address Detected Interrupt Enable */
#define ICR_ALDIE	(1 << 12)	/* Arbitratino Loss Detected Interrupt Enable */
#define ICR_SSDIE	(1 << 11)	/* Slave STOP Detected Interrupt Enable */
#define ICR_BEIE	(1 << 10)	/* Bus Error Interrupt Enable */
#define ICR_DRFIE	(1 << 9)	/* DBR Receive Full Interupt Enable */
#define ICR_ITEIE	(1 << 8)	/* IDBR Transmit Empty Interrupt Enable */
#define ICR_GCD	        (1 << 7)	/* General Call Disable */
#define ICR_IUE	        (1 << 6)	/* I2C Unit Enable */
#define ICR_SCLE	(1 << 5)	/* SCL Enable */
#define ICR_MA	        (1 << 4)	/* Master Abort */
#define ICR_TB	        (1 << 3)	/* Transfer Byte */
#define ICR_ACKNAK	(1 << 2)	/* Positive/Negative Acknowledge */
#define ICR_STOP	(1 << 1)	/* Stop */
#define ICR_START	(1 << 0)	/* Start */
            
/* I2C - Status Register */
#define ISR_BED	        (1 << 10)       /* Bus Error Detected */
#define ISR_SAD	        (1 << 9)        /* Slave Address Detected */
#define ISR_GCAD        (1 << 8)        /* General Call Address Detected */
#define ISR_IRF	        (1 << 7)        /* IDBR Receive Full */
#define ISR_ITE	        (1 << 6)        /* IDBR Transmit Empty */
#define ISR_ALD	        (1 << 5)        /* Arbitration Loss Detection */
#define ISR_SSD	        (1 << 4)        /* Slave STOP Detected */
#define ISR_IBB	        (1 << 3)        /* I2C Bus Busy */
#define ISR_UB          (1 << 2)        /* Unit Busy */
#define ISR_ACKNAK      (1 << 1)        /* Ack/Nack Status */
#define ISR_RWM         (1 << 0)        /* Read/Write Mode */

/* I2C - Bus Monitor Register */
#define IBMR_SCL        (1 << 1)        /* Continousely reflects the value of the SCL pin */
#define IBMR_SDA        (1 << 0)        /* Continousely reflects the value of the SDA pin */




/******************************************************************************/
/* I2S Controller */
/******************************************************************************/
#define SACR0	_PXAREG(0x40400000) /* Serial Audio Global Control register 14-10 */
#define SACR1	_PXAREG(0x40400004) /* Serial Audio I2S/MSB-Justified Control register 14-13 */
#define SASR0	_PXAREG(0x4040000C) /* Serial Audio I2S/MSB-Justified Interface and FIFO Status register 14-14 */
#define SAIMR	_PXAREG(0x40400014) /* Serial Audio Interrupt Mask register 14-18 */
#define SAICR	_PXAREG(0x40400018) /* Serial Audio Interrupt Clear register 14-17 */
#define SADIV	_PXAREG(0x40400060) /* Audio Clock Divider register 14-16 */
#define SADR	_PXAREG(0x40400080) /* Serial Audio Data register (TX and RX FIFO access register). 14-18 */


/******************************************************************************/
/* USB Client Controller */
/******************************************************************************/
#define UDCCR	_PXAREG(0x40600000) /* UDC Control register 12-31 */
#define UDCICR0	_PXAREG(0x40600004) /* UDC Interrupt Control register 0 12-35 */
#define UDCICR1	_PXAREG(0x40600008) /* UDC Interrupt Control register 1 12-35 */
#define UDCISR0	_PXAREG(0x4060000C) /* UDC Interrupt Status register 0 12-49 */
#define UDCISR1	_PXAREG(0x40600010) /* UDC Interrupt Status register 1 12-49 */
#define UDCFNR	_PXAREG(0x40600014) /* UDC Frame Number register 12-52 */
#define UDCOTGICR	_PXAREG(0x40600018) /* UDC OTG Interrupt Control register 12-35 */
#define UDCOTGISR	_PXAREG(0x4060001C) /* UDC OTG Interrupt Status register 12-49 */
#define UP2OCR	_PXAREG(0x40600020) /* USB Port 2 Output Control register 12-41 */
#define UP3OCR	_PXAREG(0x40600024) /* USB Port 3 Output Control register 12-47 */
#define UDCCSR0	_PXAREG(0x40600100) /* UDC Control/Status register-Endpoint 0 12-53 */
#define UDCCSRA	_PXAREG(0x40600104) /* UDC Control/Status register-Endpoint A 12-56 */
#define UDCCSRB	_PXAREG(0x40600108) /* UDC Control/Status register-Endpoint B 12-56 */
#define UDCCSRC	_PXAREG(0x4060010C) /* UDC Control/Status register-Endpoint C 12-56 */
#define UDCCSRD	_PXAREG(0x40600110) /* UDC Control/Status register-Endpoint D 12-56 */
#define UDCCSRE	_PXAREG(0x40600114) /* UDC Control/Status register-Endpoint E 12-56 */
#define UDCCSRF	_PXAREG(0x40600118) /* UDC Control/Status register-Endpoint F 12-56 */
#define UDCCSRG	_PXAREG(0x4060011C) /* UDC Control/Status register-Endpoint G 12-56 */
#define UDCCSRH	_PXAREG(0x40600120) /* UDC Control/Status register-Endpoint H 12-56 */
#define UDCCSRI	_PXAREG(0x40600124) /* UDC Control/Status register-Endpoint I 12-56 */
#define UDCCSRJ	_PXAREG(0x40600128) /* UDC Control/Status register-Endpoint J 12-56 */
#define UDCCSRK	_PXAREG(0x4060012C) /* UDC Control/Status register-Endpoint K 12-56 */
#define UDCCSRL	_PXAREG(0x40600130) /* UDC Control/Status register-Endpoint L 12-56 */
#define UDCCSRM	_PXAREG(0x40600134) /* UDC Control/Status register-Endpoint M 12-56 */
#define UDCCSRN	_PXAREG(0x40600138) /* UDC Control/Status register-Endpoint N 12-56 */
#define UDCCSRP	_PXAREG(0x4060013C) /* UDC Control/Status register-Endpoint P 12-56 */
#define UDCCSRQ	_PXAREG(0x40600140) /* UDC Control/Status register-Endpoint Q 12-56 */
#define UDCCSRR	_PXAREG(0x40600144) /* UDC Control/Status register-Endpoint R 12-56 */
#define UDCCSRS	_PXAREG(0x40600148) /* UDC Control/Status register-Endpoint S 12-56 */
#define UDCCSRT	_PXAREG(0x4060014C) /* UDC Control/Status register-Endpoint T 12-56 */
#define UDCCSRU	_PXAREG(0x40600150) /* UDC Control/Status register-Endpoint U 12-56 */
#define UDCCSRV	_PXAREG(0x40600154) /* UDC Control/Status register-Endpoint V 12-56 */
#define UDCCSRW	_PXAREG(0x40600158) /* UDC Control/Status register-Endpoint W 12-56 */
#define UDCCSRX	_PXAREG(0x4060015C) /* UDC Control/Status register-Endpoint X 12-56 */

#define UDCBCR0	_PXAREG(0x40600200) /* UDC Byte Count register-Endpoint 0 12-62 */
#define UDCBCRA	_PXAREG(0x40600204) /* UDC Byte Count register-Endpoint A 12-62 */
#define UDCBCRB	_PXAREG(0x40600208) /* UDC Byte Count register-Endpoint B 12-62 */
#define UDCBCRC	_PXAREG(0x4060020C) /* UDC Byte Count register-Endpoint C 12-62 */
#define UDCBCRD	_PXAREG(0x40600210) /* UDC Byte Count register-Endpoint D 12-62 */
#define UDCBCRE	_PXAREG(0x40600214) /* UDC Byte Count register-Endpoint E 12-62 */
#define UDCBCRF	_PXAREG(0x40600218) /* UDC Byte Count register-Endpoint F 12-62 */
#define UDCBCRG	_PXAREG(0x4060021C) /* UDC Byte Count register-Endpoint G 12-62 */
#define UDCBCRH	_PXAREG(0x40600220) /* UDC Byte Count register-Endpoint H 12-62 */
#define UDCBCRI	_PXAREG(0x40600224) /* UDC Byte Count register-Endpoint I 12-62 */
#define UDCBCRJ	_PXAREG(0x40600228) /* UDC Byte Count register-Endpoint J 12-62 */
#define UDCBCRK	_PXAREG(0x4060022C) /* UDC Byte Count register-Endpoint K 12-62 */
#define UDCBCRL	_PXAREG(0x40600230) /* UDC Byte Count register-Endpoint L 12-62 */
#define UDCBCRM	_PXAREG(0x40600234) /* UDC Byte Count register-Endpoint M 12-62 */
#define UDCBCRN	_PXAREG(0x40600238) /* UDC Byte Count register-Endpoint N 12-62 */
#define UDCBCRP	_PXAREG(0x4060023C) /* UDC Byte Count register-Endpoint P 12-62 */
#define UDCBCRQ	_PXAREG(0x40600240) /* UDC Byte Count register-Endpoint Q 12-62 */
#define UDCBCRR	_PXAREG(0x40600244) /* UDC Byte Count register-Endpoint R 12-62 */
#define UDCBCRS	_PXAREG(0x40600248) /* UDC Byte Count register-Endpoint S 12-62 */
#define UDCBCRT	_PXAREG(0x4060024C) /* UDC Byte Count register-Endpoint T 12-62 */
#define UDCBCRU	_PXAREG(0x40600250) /* UDC Byte Count register-Endpoint U 12-62 */
#define UDCBCRV	_PXAREG(0x40600254) /* UDC Byte Count register-Endpoint V 12-62 */
#define UDCBCRW	_PXAREG(0x40600258) /* UDC Byte Count register-Endpoint W 12-62 */
#define UDCBCRX	_PXAREG(0x4060025C) /* UDC Byte Count register-Endpoint X 12-62 */

#define UDCDR0	_PXAREG(0x40600300) /* UDC Data register-Endpoint 0 12-62 */
#define UDCDRA	_PXAREG(0x40600304) /* UDC Data register-Endpoint A 12-62 */
#define UDCDRB	_PXAREG(0x40600308) /* UDC Data register-Endpoint B 12-62 */
#define UDCDRC	_PXAREG(0x4060030C) /* UDC Data register-Endpoint C 12-62 */
#define UDCDRD	_PXAREG(0x40600310) /* UDC Data register-Endpoint D 12-62 */
#define UDCDRE	_PXAREG(0x40600314) /* UDC Data register-Endpoint E 12-62 */
#define UDCDRF	_PXAREG(0x40600318) /* UDC Data register-Endpoint F 12-62 */
#define UDCDRG	_PXAREG(0x4060031C) /* UDC Data register-Endpoint G 12-62 */
#define UDCDRH	_PXAREG(0x40600320) /* UDC Data register-Endpoint H 12-62 */
#define UDCDRI	_PXAREG(0x40600324) /* UDC Data register-Endpoint I 12-62 */
#define UDCDRJ	_PXAREG(0x40600328) /* UDC Data register-Endpoint J 12-62 */
#define UDCDRK	_PXAREG(0x4060032C) /* UDC Data register-Endpoint K 12-62 */
#define UDCDRL	_PXAREG(0x40600330) /* UDC Data register-Endpoint L 12-62 */
#define UDCDRM	_PXAREG(0x40600334) /* UDC Data register-Endpoint M 12-62 */
#define UDCDRN	_PXAREG(0x40600338) /* UDC Data register-Endpoint N 12-62 */
#define UDCDRP	_PXAREG(0x4060033C) /* UDC Data register-Endpoint P 12-62 */
#define UDCDRQ	_PXAREG(0x40600340) /* UDC Data register-Endpoint Q 12-62 */
#define UDCDRR	_PXAREG(0x40600344) /* UDC Data register-Endpoint R 12-62 */
#define UDCDRS	_PXAREG(0x40600348) /* UDC Data register-Endpoint S 12-62 */
#define UDCDRT	_PXAREG(0x4060034C) /* UDC Data register-Endpoint T 12-62 */
#define UDCDRU	_PXAREG(0x40600350) /* UDC Data register-Endpoint U 12-62 */
#define UDCDRV	_PXAREG(0x40600354) /* UDC Data register-Endpoint V 12-62 */
#define UDCDRW	_PXAREG(0x40600358) /* UDC Data register-Endpoint W 12-62 */
#define UDCDRX	_PXAREG(0x4060035C) /* UDC Data register-Endpoint X 12-62 */

#define UDCCRA	_PXAREG(0x40600404) /* UDC Configuration register-Endpoint A 12-64 */
#define UDCCRB	_PXAREG(0x40600408) /* UDC Configuration register-Endpoint B 12-64 */
#define UDCCRC	_PXAREG(0x4060040C) /* UDC Configuration register-Endpoint C 12-64 */
#define UDCCRD	_PXAREG(0x40600410) /* UDC Configuration register-Endpoint D 12-64 */
#define UDCCRE	_PXAREG(0x40600414) /* UDC Configuration register-Endpoint E 12-64 */
#define UDCCRF	_PXAREG(0x40600418) /* UDC Configuration register-Endpoint F 12-64 */
#define UDCCRG	_PXAREG(0x4060041C) /* UDC Configuration register-Endpoint G 12-64 */
#define UDCCRH	_PXAREG(0x40600420) /* UDC Configuration register-Endpoint H 12-64 */
#define UDCCRI	_PXAREG(0x40600424) /* UDC Configuration register-Endpoint I 12-64 */
#define UDCCRJ	_PXAREG(0x40600428) /* UDC Configuration register-Endpoint J 12-64 */
#define UDCCRK	_PXAREG(0x4060042C) /* UDC Configuration register-Endpoint K 12-64 */
#define UDCCRL	_PXAREG(0x40600430) /* UDC Configuration register-Endpoint L 12-64 */
#define UDCCRM	_PXAREG(0x40600434) /* UDC Configuration register-Endpoint M 12-64 */
#define UDCCRN	_PXAREG(0x40600438) /* UDC Configuration register-Endpoint N 12-64 */
#define UDCCRP	_PXAREG(0x4060043C) /* UDC Configuration register-Endpoint P 12-64 */
#define UDCCRQ	_PXAREG(0x40600440) /* UDC Configuration register-Endpoint Q 12-64 */