pxa27x_registers.h

tinyos2.0版本驱动

#define DRCMR19	_PXAREG(0x4000014C) /* Request to Channel Map register for STUART receive request 5-31 */
#define DRCMR20	_PXAREG(0x40000150) /* Request to Channel Map register for STUART transmit request 5-31 */
#define DRCMR21	_PXAREG(0x40000154) /* Request to Channel Map register for MMC/SDIO receive request 5-31 */
#define DRCMR22	_PXAREG(0x40000158) /* Request to Channel Map register for MMC/SDIO transmit request 5-31 */
#define DRCMR24	_PXAREG(0x40000160) /* Request to Channel Map register for USB endpoint 0 request 5-31 */
#define DRCMR25	_PXAREG(0x40000164) /* Request to Channel Map register for USB endpoint A request 5-31 */
#define DRCMR26	_PXAREG(0x40000168) /* Request to Channel Map register for USB endpoint B request 5-31 */
#define DRCMR27	_PXAREG(0x4000016C) /* Request to Channel Map register for USB endpoint C request 5-31 */
#define DRCMR28	_PXAREG(0x40000170) /* Request to Channel Map register for USB endpoint D request 5-31 */
#define DRCMR29	_PXAREG(0x40000174) /* Request to Channel Map register for USB endpoint E request 5-31 */
#define DRCMR30	_PXAREG(0x40000178) /* Request to Channel Map register for USB endpoint F request 5-31 */
#define DRCMR31	_PXAREG(0x4000017C) /* Request to Channel Map register for USB endpoint G request 5-31 */
#define DRCMR32	_PXAREG(0x40000180) /* Request to Channel Map register for USB endpoint H request 5-31 */
#define DRCMR33	_PXAREG(0x40000184) /* Request to Channel Map register for USB endpoint I request 5-31 */
#define DRCMR34	_PXAREG(0x40000188) /* Request to Channel Map register for USB endpoint J request 5-31 */
#define DRCMR35	_PXAREG(0x4000018C) /* Request to Channel Map register for USB endpoint K request 5-31 */
#define DRCMR36	_PXAREG(0x40000190) /* Request to Channel Map register for USB endpoint L request 5-31 */
#define DRCMR37	_PXAREG(0x40000194) /* Request to Channel Map register for USB endpoint M request 5-31 */
#define DRCMR38	_PXAREG(0x40000198) /* Request to Channel Map register for USB endpoint N request 5-31 */
#define DRCMR39	_PXAREG(0x4000019C) /* Request to Channel Map register for USB endpoint P request 5-31 */
#define DRCMR40	_PXAREG(0x400001A0) /* Request to Channel Map register for USB endpoint Q request 5-31 */
#define DRCMR41	_PXAREG(0x400001A4) /* Request to Channel Map register for USB endpoint R request 5-31 */
#define DRCMR42	_PXAREG(0x400001A8) /* Request to Channel Map register for USB endpoint S request 5-31 */
#define DRCMR43	_PXAREG(0x400001AC) /* Request to Channel Map register for USB endpoint T request 5-31 */
#define DRCMR44	_PXAREG(0x400001B0) /* Request to Channel Map register for USB endpoint U request 5-31 */
#define DRCMR45	_PXAREG(0x400001B4) /* Request to Channel Map register for USB endpoint V request 5-31 */
#define DRCMR46	_PXAREG(0x400001B8) /* Request to Channel Map register for USB endpoint W request 5-31 */
#define DRCMR47	_PXAREG(0x400001BC) /* Request to Channel Map register for USB endpoint X request 5-31 */
#define DRCMR48	_PXAREG(0x400001C0) /* Request to Channel Map register for MSL receive request 1 5-31 */
#define DRCMR49	_PXAREG(0x400001C4) /* Request to Channel Map register for MSL transmit request 1 5-31 */
#define DRCMR50	_PXAREG(0x400001C8) /* Request to Channel Map register for MSL receive request 2 5-31 */
#define DRCMR51	_PXAREG(0x400001CC) /* Request to Channel Map register for MSL transmit request 2 5-31 */
#define DRCMR52	_PXAREG(0x400001D0) /* Request to Channel Map register for MSL receive request 3 5-31 */
#define DRCMR53	_PXAREG(0x400001D4) /* Request to Channel Map register for MSL transmit request 3 5-31 */
#define DRCMR54	_PXAREG(0x400001D8) /* Request to Channel Map register for MSL receive request 4 5-31 */
#define DRCMR55	_PXAREG(0x400001DC) /* Request to Channel Map register for MSL transmit request 4 5-31 */
#define DRCMR56	_PXAREG(0x400001E0) /* Request to Channel Map register for MSL receive request 5 5-31 */
#define DRCMR57	_PXAREG(0x400001E4) /* Request to Channel Map register for MSL transmit request 5 5-31 */
#define DRCMR58	_PXAREG(0x400001E8) /* Request to Channel Map register for MSL receive request 6 5-31 */
#define DRCMR59	_PXAREG(0x400001EC) /* Request to Channel Map register for MSL transmit request 6 5-31 */
#define DRCMR60	_PXAREG(0x400001F0) /* Request to Channel Map register for MSL receive request 7 5-31 */
#define DRCMR61	_PXAREG(0x400001F4) /* Request to Channel Map register for MSL transmit request 7 5-31 */
#define DRCMR62	_PXAREG(0x400001F8) /* Request to Channel Map register for USIM receive request 5-31 */
#define DRCMR63	_PXAREG(0x400001FC) /* Request to Channel Map register for USIM transmit request 5-31 */

#define DDADR0	_PXAREG(0x40000200) /* DMA Descriptor Address register for Channel 0 5-32 */
#define DSADR0	_PXAREG(0x40000204) /* DMA Source Address register for Channel 0 5-33 */
#define DTADR0	_PXAREG(0x40000208) /* DMA Target Address register for Channel 0 5-34 */
#define DCMD0	_PXAREG(0x4000020C) /* DMA Command Address register for Channel 0 5-35 */
#define DDADR1	_PXAREG(0x40000210) /* DMA Descriptor Address register for Channel 1 5-32 */
#define DSADR1	_PXAREG(0x40000214) /* DMA Source Address register for Channel 1 5-33 */
#define DTADR1	_PXAREG(0x40000218) /* DMA Target Address register for Channel 1 5-34 */
#define DCMD1	_PXAREG(0x4000021C) /* DMA Command Address register for Channel 1 5-35 */
#define DDADR2	_PXAREG(0x40000220) /* DMA Descriptor Address register for Channel 2 5-32 */
#define DSADR2	_PXAREG(0x40000224) /* DMA Source Address register for Channel 2 5-33 */
#define DTADR2	_PXAREG(0x40000228) /* DMA Target Address register for Channel 2 5-34 */
#define DCMD2	_PXAREG(0x4000022C) /* DMA Command Address register for Channel 2 5-35 */
#define DDADR3	_PXAREG(0x40000230) /* DMA Descriptor Address register for Channel 3 5-32 */
#define DSADR3	_PXAREG(0x40000234) /* DMA Source Address register for Channel 3 5-33 */
#define DTADR3	_PXAREG(0x40000238) /* DMA Target Address register for Channel 3 5-34 */
#define DCMD3	_PXAREG(0x4000023C) /* DMA Command Address register for Channel 3 5-35 */
#define DDADR4	_PXAREG(0x40000240) /* DMA Descriptor Address register for Channel 4 5-32 */
#define DSADR4	_PXAREG(0x40000244) /* DMA Source Address register for Channel 4 5-33 */
#define DTADR4	_PXAREG(0x40000248) /* DMA Target Address register for Channel 4 5-34 */
#define DCMD4	_PXAREG(0x4000024C) /* DMA Command Address register for Channel 4 5-35 */
#define DDADR5	_PXAREG(0x40000250) /* DMA Descriptor Address register for Channel 5 5-32 */
#define DSADR5	_PXAREG(0x40000254) /* DMA Source Address register for Channel 5 5-33 */
#define DTADR5	_PXAREG(0x40000258) /* DMA Target Address register for Channel 5 5-34 */
#define DCMD5	_PXAREG(0x4000025C) /* DMA Command Address register for Channel 5 5-35 */
#define DDADR6	_PXAREG(0x40000260) /* DMA Descriptor Address register for Channel 6 5-32 */
#define DSADR6	_PXAREG(0x40000264) /* DMA Source Address register for Channel 6 5-33 */
#define DTADR6	_PXAREG(0x40000268) /* DMA Target Address register for Channel 6 5-34 */
#define DCMD6	_PXAREG(0x4000026C) /* DMA Command Address register for Channel 6 5-35 */
#define DDADR7	_PXAREG(0x40000270) /* DMA Descriptor Address register for Channel 7 5-32 */
#define DSADR7	_PXAREG(0x40000274) /* DMA Source Address register for Channel 7 5-33 */
#define DTADR7	_PXAREG(0x40000278) /* DMA Target Address register for Channel 7 5-34 */
#define DCMD7	_PXAREG(0x4000027C) /* DMA Command Address register for Channel 7 5-35 */
#define DDADR8	_PXAREG(0x40000280) /* DMA Descriptor Address register for Channel 8 5-32 */
#define DSADR8	_PXAREG(0x40000284) /* DMA Source Address register for Channel 8 5-33 */
#define DTADR8	_PXAREG(0x40000288) /* DMA Target Address register for Channel 8 5-34 */
#define DCMD8	_PXAREG(0x4000028C) /* DMA Command Address register for Channel 8 5-35 */
#define DDADR9	_PXAREG(0x40000290) /* DMA Descriptor Address register for Channel 9 5-32 */
#define DSADR9	_PXAREG(0x40000294) /* DMA Source Address register for Channel 9 5-33 */
#define DTADR9	_PXAREG(0x40000298) /* DMA Target Address register for Channel 9 5-34 */
#define DCMD9	_PXAREG(0x4000029C) /* DMA Command Address register for Channel 9 5-35 */
#define DDADR10	_PXAREG(0x400002A0) /* DMA Descriptor Address register for Channel 10 5-32 */
#define DSADR10	_PXAREG(0x400002A4) /* DMA Source Address register for Channel 10 5-33 */
#define DTADR10	_PXAREG(0x400002A8) /* DMA Target Address register for Channel 10 5-34 */
#define DCMD10	_PXAREG(0x400002AC) /* DMA Command Address register for Channel 10 5-35 */
#define DDADR11	_PXAREG(0x400002B0) /* DMA Descriptor Address register for Channel 11 5-32 */
#define DSADR11	_PXAREG(0x400002B4) /* DMA Source Address register for Channel 11 5-33 */
#define DTADR11	_PXAREG(0x400002B8) /* DMA Target Address register for Channel 11 5-34 */
#define DCMD11	_PXAREG(0x400002BC) /* DMA Command Address register for Channel 11 5-35 */
#define DDADR12	_PXAREG(0x400002C0) /* DMA Descriptor Address register for Channel 12 5-32 */
#define DSADR12	_PXAREG(0x400002C4) /* DMA Source Address register for Channel 12 5-33 */
#define DTADR12	_PXAREG(0x400002C8) /* DMA Target Address register for Channel 12 5-34 */
#define DCMD12	_PXAREG(0x400002CC) /* DMA Command Address register for Channel 12 5-35 */
#define DDADR13	_PXAREG(0x400002D0) /* DMA Descriptor Address register for Channel 13 5-32 */
#define DSADR13	_PXAREG(0x400002D4) /* DMA Source Address register for Channel 13 5-33 */
#define DTADR13	_PXAREG(0x400002D8) /* DMA Target Address register for Channel 13 5-34 */
#define DCMD13	_PXAREG(0x400002DC) /* DMA Command Address register for Channel 13 5-35 */
#define DDADR14	_PXAREG(0x400002E0) /* DMA Descriptor Address register for Channel 14 5-32 */
#define DSADR14	_PXAREG(0x400002E4) /* DMA Source Address register for Channel 14 5-33 */
#define DTADR14	_PXAREG(0x400002E8) /* DMA Target Address register for Channel 14 5-34 */
#define DCMD14	_PXAREG(0x400002EC) /* DMA Command Address register for Channel 14 5-35 */
#define DDADR15	_PXAREG(0x400002F0) /* DMA Descriptor Address register for Channel 15 5-32 */
#define DSADR15	_PXAREG(0x400002F4) /* DMA Source Address register for Channel 15 5-33 */
#define DTADR15	_PXAREG(0x400002F8) /* DMA Target Address register for Channel 15 5-34 */
#define DCMD15	_PXAREG(0x400002FC) /* DMA Command Address register for Channel 15 5-35 */
#define DDADR16	_PXAREG(0x40000300) /* DMA Descriptor Address register for Channel 16 5-32 */
#define DSADR16	_PXAREG(0x40000304) /* DMA Source Address register for Channel 16 5-33 */
#define DTADR16	_PXAREG(0x40000308) /* DMA Target Address register for Channel 16 5-34 */
#define DCMD16	_PXAREG(0x4000030C) /* DMA Command Address register for Channel 16 5-35 */
#define DDADR17	_PXAREG(0x40000310) /* DMA Descriptor Address register for Channel 17 5-32 */
#define DSADR17	_PXAREG(0x40000314) /* DMA Source Address register for Channel 17 5-33 */
#define DTADR17	_PXAREG(0x40000318) /* DMA Target Address register for Channel 17 5-34 */
#define DCMD17	_PXAREG(0x4000031C) /* DMA Command Address register for Channel 17 5-35 */
#define DDADR18	_PXAREG(0x40000320) /* DMA Descriptor Address register for Channel 18 5-32 */
#define DSADR18	_PXAREG(0x40000324) /* DMA Source Address register for Channel 18 5-33 */
#define DTADR18	_PXAREG(0x40000328) /* DMA Target Address register for Channel 18 5-34 */
#define DCMD18	_PXAREG(0x4000032C) /* DMA Command Address register for Channel 18 5-35 */
#define DDADR19	_PXAREG(0x40000330) /* DMA Descriptor Address register for Channel 19 5-32 */
#define DSADR19	_PXAREG(0x40000334) /* DMA Source Address register for Channel 19 5-33 */
#define DTADR19	_PXAREG(0x40000338) /* DMA Target Address register for Channel 19 5-34 */
#define DCMD19	_PXAREG(0x4000033C) /* DMA Command Address register for Channel 19 5-35 */
#define DDADR20	_PXAREG(0x40000340) /* DMA Descriptor Address register for Channel 20 5-32 */
#define DSADR20	_PXAREG(0x40000344) /* DMA Source Address register for Channel 20 5-33 */
#define DTADR20	_PXAREG(0x40000348) /* DMA Target Address register for Channel 20 5-34 */
#define DCMD20	_PXAREG(0x4000034C) /* DMA Command Address register for Channel 20 5-35 */
#define DDADR21	_PXAREG(0x40000350) /* DMA Descriptor Address register for Channel 21 5-32 */
#define DSADR21	_PXAREG(0x40000354) /* DMA Source Address register for Channel 21 5-33 */
#define DTADR21	_PXAREG(0x40000358) /* DMA Target Address register for Channel 21 5-34 */
#define DCMD21	_PXAREG(0x4000035C) /* DMA Command Address register for Channel 21 5-35 */
#define DDADR22	_PXAREG(0x40000360) /* DMA Descriptor Address register for Channel 22 5-32 */
#define DSADR22	_PXAREG(0x40000364) /* DMA Source Address register for Channel 22 5-33 */
#define DTADR22	_PXAREG(0x40000368) /* DMA Target Address register for Channel 22 5-34 */
#define DCMD22	_PXAREG(0x4000036C) /* DMA Command Address register for Channel 22 5-35 */
#define DDADR23	_PXAREG(0x40000370) /* DMA Descriptor Address register for Channel 23 5-32 */
#define DSADR23	_PXAREG(0x40000374) /* DMA Source Address register for Channel 23 5-33 */
#define DTADR23	_PXAREG(0x40000378) /* DMA Target Address register for Channel 23 5-34 */
#define DCMD23	_PXAREG(0x4000037C) /* DMA Command Address register for Channel 23 5-35 */
#define DDADR24	_PXAREG(0x40000380) /* DMA Descriptor Address register for Channel 24 5-32 */
#define DSADR24	_PXAREG(0x40000384) /* DMA Source Address register for Channel 24 5-33 */
#define DTADR24	_PXAREG(0x40000388) /* DMA Target Address register for Channel 24 5-34 */
#define DCMD24	_PXAREG(0x4000038C) /* DMA Command Address register for Channel 24 5-35 */
#define DDADR25	_PXAREG(0x40000390) /* DMA Descriptor Address register for Channel 25 5-32 */
#define DSADR25	_PXAREG(0x40000394) /* DMA Source Address register for Channel 25 5-33 */
#define DTADR25	_PXAREG(0x40000398) /* DMA Target Address register for Channel 25 5-34 */
#define DCMD25	_PXAREG(0x4000039C) /* DMA Command Address register for Channel 25 5-35 */
#define DDADR26	_PXAREG(0x400003A0) /* DMA Descriptor Address register for Channel 26 5-32 */
#define DSADR26	_PXAREG(0x400003A4) /* DMA Source Address register for Channel 26 5-33 */
#define DTADR26	_PXAREG(0x400003A8) /* DMA Target Address register for Channel 26 5-34 */
#define DCMD26	_PXAREG(0x400003AC) /* DMA Command Address register for Channel 26 5-35 */
#define DDADR27	_PXAREG(0x400003B0) /* DMA Descriptor Address register for Channel 27 5-32 */
#define DSADR27	_PXAREG(0x400003B4) /* DMA Source Address register for Channel 27 5-33 */
#define DTADR27	_PXAREG(0x400003B8) /* DMA Target Address register for Channel 27 5-34 */
#define DCMD27	_PXAREG(0x400003BC) /* DMA Command Address register for Channel 27 5-35 */
#define DDADR28	_PXAREG(0x400003C0) /* DMA Descriptor Address register for Channel 28 5-32 */
#define DSADR28	_PXAREG(0x400003C4) /* DMA Source Address register for Channel 28 5-33 */
#define DTADR28	_PXAREG(0x400003C8) /* DMA Target Address register for Channel 28 5-34 */
#define DCMD28	_PXAREG(0x400003CC) /* DMA Command Address register for Channel 28 5-35 */
#define DDADR29	_PXAREG(0x400003D0) /* DMA Descriptor Address register for Channel 29 5-32 */
#define DSADR29	_PXAREG(0x400003D4) /* DMA Source Address register for Channel 29 5-33 */
#define DTADR29	_PXAREG(0x400003D8) /* DMA Target Address register for Channel 29 5-34 */
#define DCMD29	_PXAREG(0x400003DC) /* DMA Command Address register for Channel 29 5-35 */
#define DDADR30	_PXAREG(0x400003E0) /* DMA Descriptor Address register for Channel 30 5-32 */
#define DSADR30	_PXAREG(0x400003E4) /* DMA Source Address register for Channel 30 5-33 */
#define DTADR30	_PXAREG(0x400003E8) /* DMA Target Address register for Channel 30 5-34 */
#define DCMD30	_PXAREG(0x400003EC) /* DMA Command Address register for Channel 30 5-35 */
#define DDADR31	_PXAREG(0x400003F0) /* DMA Descriptor Address register for Channel 31 5-32 */
#define DSADR31	_PXAREG(0x400003F4) /* DMA Source Address register for Channel 31 5-33 */
#define DTADR31	_PXAREG(0x400003F8) /* DMA Target Address register for Channel 31 5-34 */
#define DCMD31	_PXAREG(0x400003FC) /* DMA Command Address register for Channel 31 5-35 */

#define DRCMR64	_PXAREG(0x40001100) /* Request to Channel Map register for Memory Stick receive request 5-31 */
#define DRCMR65	_PXAREG(0x40001104) /* Request to Channel Map register for Memory Stick transmit request 5-31 */
#define DRCMR66	_PXAREG(0x40001108) /* Request to Channel Map register for SSP3 receive request 5-31 */
#define DRCMR67	_PXAREG(0x4000110C) /* Request to Channel Map register for SSP3 transmit request 5-31 */
#define DRCMR68	_PXAREG(0x40001110) /* Request to Channel Map register for Quick Capture Interface Receive Request 0 5-31 */
#define DRCMR69	_PXAREG(0x40001114) /* Request to Channel Map register for Quick Capture Interface Receive Request 1 5-31 */
#define DRCMR70	_PXAREG(0x40001118) /* Request to Channel Map register for Quick Capture Interface Receive Request 2 5-31 */

#define DRCMR74	_PXAREG(0x40001128) /* Request to Channel Map register for DREQ<2> (companion chip request 2) 5-31 */

#define FLYCNFG	_PXAREG(0x48000020) /* Fly-by DMA DVAL<1:0> polarities 5-39 */

// DMA Register shortcuts
#define DCSR(_ch)  _PXAREG_OFFSET(&DCSR0,((_ch) << 2))
#define DRQSR(_line) _PXAREG_OFFSET(&DRQSR0,((_line) << 2))
#define DRCMR(_dev) *(((_dev) < 63) ? (&_PXAREG_OFFSET(&DRCMR0, (((_dev) & 0x3f) << 2))) \
				   : (&_PXAREG_OFFSET(&DRCMR64,(((_dev) & 0x3f) << 2))))
#define DDADR(_ch) _PXAREG_OFFSET(&DDADR0,((_ch) << 4))
#define DSADR(_ch) _PXAREG_OFFSET(&DSADR0,((_ch) << 4))
#define DTADR(_ch) _PXAREG_OFFSET(&DTADR0,((_ch) << 4))
#define DCMD(_ch) _PXAREG_OFFSET(&DCMD0,((_ch) << 4))


#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */