pxa27x_registers.h

tinyos2.0版本驱动

#define LDCMD1	_PXAREG(0x4400021C) /* LCD DMA Channel 1 Command register 7-118 */
#define FDADR2	_PXAREG(0x44000220) /* DMA Channel 2 Frame Descriptor Address register 7-100 */
#define FSADR2	_PXAREG(0x44000224) /* DMA Channel 2 Frame Source Address register 7-117 */
#define FIDR2	_PXAREG(0x44000228) /* DMA Channel 2 Frame ID register 7-117 */
#define LDCMD2	_PXAREG(0x4400022C) /* LCD DMA Channel 2 Command register 7-118 */
#define FDADR3	_PXAREG(0x44000230) /* DMA Channel 3 Frame Descriptor Address register 7-100 */
#define FSADR3	_PXAREG(0x44000234) /* DMA Channel 3 Frame Source Address register 7-117 */
#define FIDR3	_PXAREG(0x44000238) /* DMA Channel 3 Frame ID register 7-117 */
#define LDCMD3	_PXAREG(0x4400023C) /* LCD DMA Channel 3 Command register 7-118 */
#define FDADR4	_PXAREG(0x44000240) /* DMA Channel 4 Frame Descriptor Address register 7-100 */
#define FSADR4	_PXAREG(0x44000244) /* DMA Channel 4 Frame Source Address register 7-117 */
#define FIDR4	_PXAREG(0x44000248) /* DMA Channel 4 Frame ID register 7-117 */
#define LDCMD4	_PXAREG(0x4400024C) /* LCD DMA Channel 4 Command register 7-118 */
#define FDADR5	_PXAREG(0x44000250) /* DMA Channel 5 Frame Descriptor Address register 7-100 */
#define FSADR5	_PXAREG(0x44000254) /* DMA Channel 5 Frame Source Address register 7-117 */
#define FIDR5	_PXAREG(0x44000258) /* DMA Channel 5 Frame ID register 7-117 */
#define LDCMD5	_PXAREG(0x4400025C) /* LCD DMA Channel 5 Command register 7-118 */
#define FDADR6	_PXAREG(0x44000260) /* DMA Channel 6 Frame Descriptor Address register 7-100 */
#define FSADR6	_PXAREG(0x44000264) /* DMA Channel 6 Frame Source Address register 7-117 */
#define FIDR6	_PXAREG(0x44000268) /* DMA Channel 6 Frame ID register 7-117 */
#define LDCMD6	_PXAREG(0x4400026C) /* LCD DMA Channel 6 Command register 7-118 */
#define LCDBSCNTR	_PXAREG(0x48000054) /* LCD Buffer Strength Control register 7-102 */


/******************************************************************************/
/* USB Host Controller */
/******************************************************************************/
#define UHCREV	_PXAREG(0x4C000000) /* UHC HCI Spec Revision register 20-10 */
#define UHCHCON	_PXAREG(0x4C000004) /* UHC Host Control register 20-10 */
#define UHCCOMS	_PXAREG(0x4C000008) /* UHC Command Status register 20-14 */
#define UHCINTS	_PXAREG(0x4C00000C) /* UHC Interrupt Status register 20-16 */
#define UHCINTE	_PXAREG(0x4C000010) /* UHC Interrupt Enable register 20-18 */
#define UHCINTD	_PXAREG(0x4C000014) /* UHC Interrupt Disable register 20-20 */
#define UHCHCCA	_PXAREG(0x4C000018) /* UHC Host Controller Communication Area register 20-21 */
#define UHCPCED	_PXAREG(0x4C00001C) /* UHC Period Current Endpoint Descriptor register 20-21 */
#define UHCCHED	_PXAREG(0x4C000020) /* UHC Control Head Endpoint Descriptor register 20-22 */
#define UHCCCED	_PXAREG(0x4C000024) /* UHC Control Current Endpoint Descriptor register 20-22 */
#define UHCBHED	_PXAREG(0x4C000028) /* UHC Bulk Head Endpoint Descriptor register 20-23 */
#define UHCBCED	_PXAREG(0x4C00002C) /* UHC Bulk Current Endpoint Descriptor register 20-24 */
#define UHCDHEAD	_PXAREG(0x4C000030) /* UHC Done Head register 20-25 */
#define UHCFMI	_PXAREG(0x4C000034) /* UHC Frame Interval register 20-26 */
#define UHCFMR	_PXAREG(0x4C000038) /* UHC Frame Remaining register 20-27 */
#define UHCFMN	_PXAREG(0x4C00003C) /* UHC Frame Number register 20-28 */
#define UHCPERS	_PXAREG(0x4C000040) /* UHC Periodic Start register 20-29 */
#define UHCLST	_PXAREG(0x4C000044) /* UHC Low-Speed Threshold register 20-30 */
#define UHCRHDA	_PXAREG(0x4C000048) /* UHC Root Hub Descriptor A register 20-31 */
#define UHCRHDB	_PXAREG(0x4C00004C) /* UHC Root Hub Descriptor B register 20-33 */
#define UHCRHS	_PXAREG(0x4C000050) /* UHC Root Hub Status register 20-34 */
#define UHCRHPS1	_PXAREG(0x4C000054) /* UHC Root Hub Port 1 Status register 20-35 */
#define UHCRHPS2	_PXAREG(0x4C000058) /* UHC Root Hub Port 2 Status register 20-35 */
#define UHCRHPS3	_PXAREG(0x4C00005C) /* UHC Root Hub Port 3 Status register 20-35 */
#define UHCSTAT	_PXAREG(0x4C000060) /* UHC Status register 20-39 */
#define UHCHR	_PXAREG(0x4C000064) /* UHC Reset register 20-41 */
#define UHCHIE	_PXAREG(0x4C000068) /* UHC Interrupt Enable register 20-44 */
#define UHCHIT	_PXAREG(0x4C00006C) /* UHC Interrupt Test register 20-45 */


/******************************************************************************/
/* Quick Capture Interface */
/******************************************************************************/
#define CICR0	_PXAREG(0x50000000) /* Quick Capture Interface Control register 0 27-24 */
#define CICR1	_PXAREG(0x50000004) /* Quick Capture Interface Control register 1 27-28 */
#define CICR2	_PXAREG(0x50000008) /* Quick Capture Interface Control register 2 27-32 */
#define CICR3	_PXAREG(0x5000000C) /* Quick Capture Interface Control register 3 27-33 */
#define CICR4	_PXAREG(0x50000010) /* Quick Capture Interface Control register 4 27-34 */
#define CISR	_PXAREG(0x50000014) /* Quick Capture Interface Status register 27-37 */
#define CIFR	_PXAREG(0x50000018) /* Quick Capture Interface FIFO Control register 27-40 */
#define CITOR	_PXAREG(0x5000001C) /* Quick Capture Interface Time-Out register 27-37 */
#define CIBR0	_PXAREG(0x50000028) /* Quick Capture Interface Receive Buffer register 0 (Channel 0) 27-42 */
#define CIBR1	_PXAREG(0x50000030) /* Quick Capture Interface Receive Buffer register 1 (Channel 1) 27-42 */
#define CIBR2	_PXAREG(0x50000038) /* Quick Capture Interface Receive Buffer register 2 (Channel 2) 27-42 */


/* Quick Capture Interface - Control Register 0 */
#define CICR0_DMA_EN    (1 << 31)	/* DMA Request Enable */
#define CICR0_EN        (1 << 28)	/* Quick Capture Interface Enable (and Quick Disable) */
#define CICR0_TOM       (1 << 9)	/* Time-Out Interrupt Mask */
#define CICR0_RDAVM     (1 << 8)	/* Receive-Data-Available Interrupt Mask */
#define CICR0_FEM       (1 << 7)	/* FIFO-Empty Interrupt Mask */
#define CICR0_EOLM      (1 << 6)	/* End-of-Line Interrupt Mask */
#define CICR0_SOFM      (1 << 2)	/* Start-of-Frame Interrupt Mask */
#define CICR0_EOFM      (1 << 1)	/* End-of-Frame Interrupt Mask */
#define CICR0_FOM       (1 << 0)	/* FIFO Overrun Interrupt Mask */


/* Quick Capture Interface - Control Register 1 */
#define CICR1_TBIT      (1 << 31)   /* Transparency Bit */
#define CICR1_RGBT_CONV(_data,_x)   ((_data & ~(0x7 << 29)) | (_x << 29))       /* RGBT Conversion */
#define CICR1_PPL(_data,_x)         ((_data & ~(0x7ff << 15)) | (_x << 15))     /* Pixels per Line */
#define CICR1_RGB_CONV(_data,_x)    ((_data & ~(0x7 << 12)) | (_x << 12))       /* RGB Bits per Pixel Conversion */
#define CICR1_RGB_F     (1 << 11)   /* RGB Format */
#define CICR1_YCBCR_F   (1 << 10)   /* YCbCr Format */
#define CICR1_RGB_BPP(_data,_x)     ((_data & ~(0x7 << 7)) | (_x << 7))         /* RGB Bits per Pixel */
#define CICR1_RAW_BPP(_data,_x)     ((_data & ~(0x3 << 5)) | (_x << 5))         /* Raw Bits per Pixel */
#define CICR1_COLOR_SP(_data,_x)    ((_data & ~(0x3 << 3)) | (_x << 3))         /* Color Space */
#define CICR1_DW(_data,_x)          ((_data & ~(0x7 << 0)) | (_x << 0))         /* Data Width */


/* Quick Capture Interface - Control Register 3 */
#define CICR3_LPF(_data,_x)	        ((_data & ~(0x7ff << 0)) | (_x << 0))       /* Lines per Frame */
                                               
/* Quick Capture Interface - Control Register 4 */
#define CICR4_PCLK_EN   (1 << 23)   /* Pixel Clock Enable */
#define CICR4_HSP       (1 << 21)	/* Horizontal Sync Polarity */
#define CICR4_VSP       (1 << 20)	/* Vertical Sync Polarity */
#define CICR4_MCLK_EN   (1 << 19)	/* MCLK Enable */
#define CICR4_DIV(_data,_x)         ((_data & ~(0xff << 0)) | (_x << 0))        /* Clock Divisor */

/* Quick Capture Interface - Status Register */
#define CISR_FTO        (1 << 15)	/* FIFO Time-Out */
#define CISR_RDAV_2     (1 << 14)	/* Channel 2 Receive Data Available */
#define CISR_RDAV_1     (1 << 13)	/* Channel 1 Receive Data Available */
#define CISR_RDAV_0     (1 << 12)	/* Channel 0 Receive Data Available */
#define CISR_FEMPTY_2   (1 << 11)	/* Channel 2 FIFO Empty */
#define CISR_FEMPTY_1   (1 << 10)	/* Channel 1 FIFO Empty */
#define CISR_FEMPTY_0   (1 << 9)	/* Channel 0 FIFO Empty */
#define CISR_EOL        (1 << 8)	/* End-of-Line */
#define CISR_PAR_ERR    (1 << 7)	/* Parity Error */
#define CISR_CQD        (1 << 6)	/* Quick Campture Interface Quick Dissable */
#define CISR_CDD        (1 << 5)	/* Quick Campture Interface Quick Dissable Done */
#define CISR_SOF        (1 << 4)	/* Start-of-Frame */
#define CISR_EOF        (1 << 3)	/* End-of-Frame */
#define CISR_IFO_2      (1 << 2)	/* FIFO Overrun for Channel 2 */
#define CISR_IFO_1      (1 << 1)	/* FIFO Overrun for Channel 1 */
#define CISR_IFO_0      (1 << 0)	/* FIFO Overrun for Channel 0 */


/* Quick Capture Interface - FIFO Control Register */
#define CIFR_FLVL0(_data,_x)        ((_data & ~(0xff << 8)) | (_x << 8))        /* FIFO 0 Level: value from 0-128 indicates the number of bytes */
#define CIFR_THL_0(_data,_x)        ((_data & ~(0x3 << 4)) | (_x << 4))         /* Threshold Level for Channel 0 FIFO */
#define CIFR_RESETF     (1 << 3)	/* Reset input FIFOs */




/******************************************************************************/
/* DMA Controller */
/******************************************************************************/
#define DCSR0	_PXAREG(0x40000000) /* DMA Control/Status register for Channel 0 5-41 */
#define DCSR1	_PXAREG(0x40000004) /* DMA Control/Status register for Channel 1 5-41 */
#define DCSR2	_PXAREG(0x40000008) /* DMA Control/Status register for Channel 2 5-41 */
#define DCSR3	_PXAREG(0x4000000C) /* DMA Control/Status register for Channel 3 5-41 */
#define DCSR4	_PXAREG(0x40000010) /* DMA Control/Status register for Channel 4 5-41 */
#define DCSR5	_PXAREG(0x40000014) /* DMA Control/Status register for Channel 5 5-41 */
#define DCSR6	_PXAREG(0x40000018) /* DMA Control/Status register for Channel 6 5-41 */
#define DCSR7	_PXAREG(0x4000001C) /* DMA Control/Status register for Channel 7 5-41 */
#define DCSR8	_PXAREG(0x40000020) /* DMA Control/Status register for Channel 8 5-41 */
#define DCSR9	_PXAREG(0x40000024) /* DMA Control/Status register for Channel 9 5-41 */
#define DCSR10	_PXAREG(0x40000028) /* DMA Control/Status register for Channel 10 5-41 */
#define DCSR11	_PXAREG(0x4000002C) /* DMA Control/Status register for Channel 11 5-41 */
#define DCSR12	_PXAREG(0x40000030) /* DMA Control/Status register for Channel 12 5-41 */
#define DCSR13	_PXAREG(0x40000034) /* DMA Control/Status register for Channel 13 5-41 */
#define DCSR14	_PXAREG(0x40000038) /* DMA Control/Status register for Channel 14 5-41 */
#define DCSR15	_PXAREG(0x4000003C) /* DMA Control/Status register for Channel 15 5-41 */
#define DCSR16	_PXAREG(0x40000040) /* DMA Control/Status register for Channel 16 5-41 */
#define DCSR17	_PXAREG(0x40000044) /* DMA Control/Status register for Channel 17 5-41 */
#define DCSR18	_PXAREG(0x40000048) /* DMA Control/Status register for Channel 18 5-41 */
#define DCSR19	_PXAREG(0x4000004C) /* DMA Control/Status register for Channel 19 5-41 */
#define DCSR20	_PXAREG(0x40000050) /* DMA Control/Status register for Channel 20 5-41 */
#define DCSR21	_PXAREG(0x40000054) /* DMA Control/Status register for Channel 21 5-41 */
#define DCSR22	_PXAREG(0x40000058) /* DMA Control/Status register for Channel 22 5-41 */
#define DCSR23	_PXAREG(0x4000005C) /* DMA Control/Status register for Channel 23 5-41 */
#define DCSR24	_PXAREG(0x40000060) /* DMA Control/Status register for Channel 24 5-41 */
#define DCSR25	_PXAREG(0x40000064) /* DMA Control/Status register for Channel 25 5-41 */
#define DCSR26	_PXAREG(0x40000068) /* DMA Control/Status register for Channel 26 5-41 */
#define DCSR27	_PXAREG(0x4000006C) /* DMA Control/Status register for Channel 27 5-41 */
#define DCSR28	_PXAREG(0x40000070) /* DMA Control/Status register for Channel 28 5-41 */
#define DCSR29	_PXAREG(0x40000074) /* DMA Control/Status register for Channel 29 5-41 */
#define DCSR30	_PXAREG(0x40000078) /* DMA Control/Status register for Channel 30 5-41 */
#define DCSR31	_PXAREG(0x4000007C) /* DMA Control/Status register for Channel 31 5-41 */

#define DALGN	_PXAREG(0x400000A0) /* DMA Alignment register 5-49 */
#define DPCSR	_PXAREG(0x400000A4) /* DMA Programmed I/O Control Status register 5-51 */

#define DRQSR0	_PXAREG(0x400000E0) /* DMA DREQ<0> Status register 5-40 */
#define DRQSR1	_PXAREG(0x400000E4) /* DMA DREQ<1> Status register 5-40 */
#define DRQSR2	_PXAREG(0x400000E8) /* DMA DREQ<2> Status register 5-40 */

#define DINT	_PXAREG(0x400000F0) /* DMA Interrupt register 5-48 */

#define DRCMR0	_PXAREG(0x40000100) /* Request to Channel Map register for DREQ<0> (companion chip request 0) 5-31 */
#define DRCMR1	_PXAREG(0x40000104) /* Request to Channel Map register for DREQ<1> (companion chip request 1) 5-31 */
#define DRCMR2	_PXAREG(0x40000108) /* Request to Channel Map register for I2S receive request 5-31 */
#define DRCMR3	_PXAREG(0x4000010C) /* Request to Channel Map register for I2S transmit request 5-31 */
#define DRCMR4	_PXAREG(0x40000110) /* Request to Channel Map register for BTUART receive request 5-31 */
#define DRCMR5	_PXAREG(0x40000114) /* Request to Channel Map register for BTUART transmit request. 5-31 */
#define DRCMR6	_PXAREG(0x40000118) /* Request to Channel Map register for FFUART receive request 5-31 */
#define DRCMR7	_PXAREG(0x4000011C) /* Request to Channel Map register for FFUART transmit request 5-31 */
#define DRCMR8	_PXAREG(0x40000120) /* Request to Channel Map register for AC 97 microphone request 5-31 */
#define DRCMR9	_PXAREG(0x40000124) /* Request to Channel Map register for AC 97 modem receive request 5-31 */
#define DRCMR10	_PXAREG(0x40000128) /* Request to Channel Map register for AC 97 modem transmit request 5-31 */
#define DRCMR11	_PXAREG(0x4000012C) /* Request to Channel Map register for AC 97 audio receive request 5-31 */
#define DRCMR12	_PXAREG(0x40000130) /* Request to Channel Map register for AC 97 audio transmit request 5-31 */
#define DRCMR13	_PXAREG(0x40000134) /* Request to Channel Map register for SSP1 receive request 5-31 */
#define DRCMR14	_PXAREG(0x40000138) /* Request to Channel Map register for SSP1 transmit request 5-31 */
#define DRCMR15	_PXAREG(0x4000013C) /* Request to Channel Map register for SSP2 receive request 5-31 */
#define DRCMR16	_PXAREG(0x40000140) /* Request to Channel Map register for SSP2 transmit request 5-31 */
#define DRCMR17	_PXAREG(0x40000144) /* Request to Channel Map register for ICP receive request 5-31 */
#define DRCMR18	_PXAREG(0x40000148) /* Request to Channel Map register for ICP transmit request 5-31 */