pxa27x_registers.h

tinyos2.0版本驱动

// $Id: pxa27x_registers.h,v 1.5 2008/06/11 00:46:23 razvanm Exp $ 

/*
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 *  this license.  If you do not agree to this license, do not download,
 *  install, copy or use the software.
 *
 *  Intel Open Source License 
 *
 *  Copyright (c) 2002 Intel Corporation 
 *  All rights reserved. 
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 *  modification, are permitted provided that the following conditions are
 *  met:
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 *	Redistributions of source code must retain the above copyright
 *  notice, this list of conditions and the following disclaimer.
 *	Redistributions in binary form must reproduce the above copyright
 *  notice, this list of conditions and the following disclaimer in the
 *  documentation and/or other materials provided with the distribution.
 *      Neither the name of the Intel Corporation nor the names of its
 *  contributors may be used to endorse or promote products derived from
 *  this software without specific prior written permission.
 *  
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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/*
 *
 * Authors:		Phil Buonadonna
 *
 * Edits:	Josh Herbach, Konrad Lorincz
 * Revised: 09/19/2005
 */

#ifndef _PXA27X_REGISTER_H
#define _PXA27X_REGISTER_H


#define _PXAREG(_addr)	(*((volatile uint32_t *)(_addr)))
#define _PXAREG_OFFSET(_addr,_off) (_PXAREG((uint32_t)(_addr) + (uint32_t)(_off)))

					
/******************************************************************************/
/* Memory Controller */
/******************************************************************************/
#define MDCNFG	_PXAREG(0x48000000) /* SDRAM Configuration register 6-43 */
#define MDREFR	_PXAREG(0x48000004) /* SDRAM Refresh Control register 6-53 */
#define MSC0	_PXAREG(0x48000008) /* Static Memory Control register 0 6-63 */
#define MSC1	_PXAREG(0x4800000C) /* Static Memory Control register 1 6-63 */
#define MSC2	_PXAREG(0x48000010) /* Static Memory Control register 2 6-63 */
#define MECR	_PXAREG(0x48000014) /* Expansion Memory (PC Card/CompactFlash) Bus Configuration register 6-79 */
#define SXCNFG	_PXAREG(0x4800001C) /* Synchronous Static Memory Configuration register 6-58 */
#define FLYCNFG	_PXAREG(0x48000020) /* Fly-by DMA DVAL<1:0> polarities 5-39 */
#define MCMEM0	_PXAREG(0x48000028) /* PC Card Interface Common Memory Space Socket 0 Timing Configuration register 6-77 */
#define MCMEM1	_PXAREG(0x4800002C) /* PC Card Interface Common Memory Space Socket 1 Timing Configuration register 6-77 */
#define MCATT0	_PXAREG(0x48000030) /* PC Card Interface Attribute Space Socket 0 Timing Configuration register 6-77 */
#define MCATT1	_PXAREG(0x48000034) /* PC Card Interface Attribute Space Socket 1 Timing Configuration register 6-77 */
#define MCIO0	_PXAREG(0x48000038) /* PC Card Interface I/o Space Socket 0 Timing Configuration register 6-78 */
#define MCIO1	_PXAREG(0x4800003C) /* PC Card Interface I/o Space Socket 1 Timing Configuration register 6-78 */
#define MDMRS	_PXAREG(0x48000040) /* SDRAM Mode Register Set Configuration register 6-49 */
#define BOOT_DEF	_PXAREG(0x48000044) /* Boot Time Default Configuration register 6-75 */
#define ARB_CNTL	_PXAREG(0x48000048) /* Arbiter Control register 29-2 */
#define BSCNTR0	_PXAREG(0x4800004C) /* System Memory Buffer Strength Control register 0 6-81 */
#define BSCNTR1	_PXAREG(0x48000050) /* System Memory Buffer Strength Control register 1 6-82 */
#define LCDBSCNTR	_PXAREG(0x48000054) /* LCD Buffer Strength Control register 7-102 */
#define MDMRSLP	_PXAREG(0x48000058) /* Special Low Power SDRAM Mode Register Set Configuration register 6-51 */
#define BSCNTR2	_PXAREG(0x4800005C) /* System Memory Buffer Strength Control register 2 6-83 */
#define BSCNTR3	_PXAREG(0x48000060) /* System Memory Buffer Strength Control register 3 6-84 */
#define SA1110	_PXAREG(0x48000064) /* SA-1110 Compatibility Mode for Static Memory register 6-70 */

/* MDCNFG Bit Defs */
#define MDCNFG_MDENX		(1 << 31)
#define MDCNFG_DCACX2		(1 << 30)
#define MDCNFG_DSA1110_2	(1 << 28)
#define MDCNFG_DADDR2		(1 << 26)
#define MDCNFG_DTC2(_x)		(((_x) & 0x3) << 24)
#define MDCNFG_DNB2		(1 << 23)
#define MDCNFG_DRAC2(_x)	(((_x) & 0x3) << 21)
#define MDCNFG_DCAC2(_x)	(((_x) & 0x3) << 19)
#define MDCNFG_DWID2		(1 << 18)
#define MDCNFG_DE3		(1 << 17)
#define MDCNFG_DE2		(1 << 16)
#define MDCNFG_STACK1		(1 << 15)
#define MDCNFG_DCACX0		(1 << 14)
#define MDCNFG_STACK0		(1 << 13)
#define MDCNFG_DSA1110_0	(1 << 12)
#define MDCNFG_DADDR0		(1 << 10)
#define MDCNFG_DTC0(_x)		(((_x) & 0x3) << 8)
#define MDCNFG_DNB0		(1 << 7)
#define MDCNFG_DRAC0(_x)	(((_x) & 0x3) << 5)
#define MDCNFG_DCAC0(_x)	(((_x) & 0x3) << 3)
#define MDCNFG_DWID0		(1 << 2)
#define MDCNFG_DE1		(1 << 1)
#define MDCNFG_DE0		(1 << 0)
#define MDCNFG_SETALWAYS	((1 << 27) | (1 << 11))

/* MDREFR Bit Defs */
#define MDREFR_ALTREFA	(1 << 31)	/* */
#define MDREFR_ALTREFB	(1 << 30)	/* */
#define MDREFR_K0DB4	(1 << 29)	/* */
#define MDREFR_K2FREE	(1 << 25)	/* */
#define MDREFR_K1FREE	(1 << 24)	/* */
#define MDREFR_K0FREE	(1 << 23)	/* */
#define MDREFR_SLFRSH	(1 << 22)	/* */
#define MDREFR_APD	(1 << 20)	/* */
#define MDREFR_K2DB2	(1 << 19)	/* */
#define MDREFR_K2RUN	(1 << 18)	/* */
#define MDREFR_K1DB2	(1 << 17)	/* */
#define MDREFR_K1RUN	(1 << 16)	/* */
#define MDREFR_E1PIN	(1 << 15)	/* */
#define MDREFR_K0DB2	(1 << 14)	/* */
#define MDREFR_K0RUN	(1 << 13)	/* */
#define MDREFR_DRI(_x)  ((_x) & 0xfff) /* */

/* MSCx Bit Defs */
#define MSC_RBUFF135	(1 << 31)		 /* Return Data Buff vs. Streaming  nCS 1,3 or 5 */
#define MSC_RRR135(_x)	(((_x) & (0x7)) << 28)	/* ROM/SRAM Recovery Time  nCS 1,3 or 5 */
#define MSC_RDN135(_x)	(((_x) & (0x7)) << 24)	/* ROM Delay Next Access nCS 1,3 or 5 */
#define MSC_RDF135(_x)	(((_x) & (0x7)) << 20)	/* ROM Delay First Access nCS 1,3 or 5 */
#define MSC_RBW135	(1 << 19)		/* ROM Bus Width nCS 1,3 or 5 */
#define MSC_RT135(_x)	(((_x) & (0x7)) << 16)	/* ROM Type  nCS 1,3 or 5 */
#define MSC_RBUFF024	(1 << 15)		/* Return Data Buff vs. Streaming  nCS 0,2 or 4 */
#define MSC_RRR024(_x)	(((_x) & (0x7)) << 12)	/* ROM/SRAM Recover Time  nCS 0,2 or 4 */
#define MSC_RDN024(_x)	(((_x) & (0x7)) << 8)	/* ROM Delay Next Access  nCS 0,2 or 4 */
#define MSC_RDF024(_x)	(((_x) & (0x7)) << 4)	/* ROM Delay First Access  nCS 0,2 or 4 */
#define MSC_RBW024	(1 << 3)		/* ROM Bus Width  nCS 0,2 or 4 */
#define MSC_RT024(_x)	(((_x) & (0x7)) << 0)	/* ROM Type  nCS 0,2 or 4 */

/* SXCNFG Bit defs */
#define SXCNFG_SXEN0 (1)
#define SXCNFG_SXEN1 (1<<1)
#define SXCNFG_SXCL0(_x) (((_x) & 0x7) << 2)
#define SXCNFG_SXTP0(_x) (((_x) & 0x3) << 12)
#define SXCNFG_SXCLEXT0 (1<<15)

/* ARB_CNTL Bit defs */
#define ARB_CNTL_DMA_SLV_PARK (1 << 31) 
#define ARB_CNTL_CI_PARK (1 << 30) 
#define ARB_CNTL_EX_MEM_PARK (1 << 29) 
#define ARB_CNTL_INT_MEM_PARK (1 << 28) 
#define ARB_CNTL_USB_PARK (1 << 27) 
#define ARB_CNTL_LCD_PARK (1 << 26) 
#define ARB_CNTL_DMA_PARK (1 << 25) 
#define ARB_CNTL_CORE_PARK (1 << 24) 
#define ARB_CNTL_LOCK_FLAG (1 << 23) 
#define ARB_CNTL_LCD_WT(_wt) (((_wt) & 0xF) << 8)
#define ARB_CNTL_DMA_WT(_wt) (((_wt) & 0xF) << 4)
#define ARB_CNTL_CORE_WT(_wt) (((_wt) & 0xF) << 0)

/* SA1110 Bit defs */
#define SA1110_SXSTACK(_x) (((_x) & 0x3) << 12)
/******************************************************************************/
/* LCD Controller */
/******************************************************************************/
#define LCCR0	_PXAREG(0x44000000) /* LCD Controller Control register 0 7-56 */
#define LCCR1	_PXAREG(0x44000004) /* LCD Controller Control register 1 7-64 */
#define LCCR2	_PXAREG(0x44000008) /* LCD Controller Control register 2 7-66 */
#define LCCR3	_PXAREG(0x4400000C) /* LCD Controller Control register 3 7-69 */
#define LCCR4	_PXAREG(0x44000010) /* LCD Controller Control register 4 7-74 */
#define LCCR5	_PXAREG(0x44000014) /* LCD Controller Control register 5 7-77 */
#define FBR0	_PXAREG(0x44000020) /* DMA Channel 0 Frame Branch register 7-101 */
#define FBR1	_PXAREG(0x44000024) /* DMA Channel 1 Frame Branch register 7-101 */
#define FBR2	_PXAREG(0x44000028) /* DMA Channel 2 Frame Branch register 7-101 */
#define FBR3	_PXAREG(0x4400002C) /* DMA Channel 3 Frame Branch register 7-101 */
#define FBR4	_PXAREG(0x44000030) /* DMA Channel 4 Frame Branch register 7-101 */
#define LCSR1	_PXAREG(0x44000034) /* LCD Controller Status register 1 7-109 */
#define LCSR0	_PXAREG(0x44000038) /* LCD Controller Status register 0 7-104 */
#define LIIDR	_PXAREG(0x4400003C) /* LCD Controller Interrupt ID register 7-116 */
#define TRGBR	_PXAREG(0x44000040) /* TMED RGB Seed register 7-97 */
#define TCR	_PXAREG(0x44000044) /* TMED Control register 7-98 */
#define OVL1C1	_PXAREG(0x44000050) /* Overlay 1 Control register 1 7-90 */
#define OVL1C2	_PXAREG(0x44000060) /* Overlay 1 Control register 2 7-91 */
#define OVL2C1	_PXAREG(0x44000070) /* Overlay 2 Control register 1 7-92 */
#define OVL2C2	_PXAREG(0x44000080) /* Overlay 2 Control register 2 7-94 */
#define CCR	_PXAREG(0x44000090) /* Cursor Control register 7-95 */
#define CMDCR	_PXAREG(0x44000100) /* Command Control register 7-96 */
#define PRSR	_PXAREG(0x44000104) /* Panel Read Status register 7-103 */
#define FBR5	_PXAREG(0x44000110) /* DMA Channel 5 Frame Branch register 7-101 */
#define FBR6	_PXAREG(0x44000114) /* DMA Channel 6 Frame Branch register 7-101 */
#define FDADR0	_PXAREG(0x44000200) /* DMA Channel 0 Frame Descriptor Address register 7-100 */
#define FSADR0	_PXAREG(0x44000204) /* DMA Channel 0 Frame Source Address register 7-117 */
#define FIDR0	_PXAREG(0x44000208) /* DMA Channel 0 Frame ID register 7-117 */
#define LDCMD0	_PXAREG(0x4400020C) /* LCD DMA Channel 0 Command register 7-118 */
#define FDADR1	_PXAREG(0x44000210) /* DMA Channel 1 Frame Descriptor Address register 7-100 */
#define FSADR1	_PXAREG(0x44000214) /* DMA Channel 1 Frame Source Address register 7-117 */
#define FIDR1	_PXAREG(0x44000218) /* DMA Channel 1 Frame ID register 7-117 */