_primary.vhd

来自「该源码为xilinx ise教程的附带光盘源码」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity cntr_rtl is
    port(
        d               : in     vl_logic_vector(3 downto 0);
        ld              : in     vl_logic;
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        q               : out    vl_logic_vector(3 downto 0)
    );
end cntr_rtl;