prescale_counter.par

该源码为xilinx ise教程的附带光盘源码

Release 9.1i par J.30
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

ZHONGXCH::  Tue Dec 12 15:37:54 2006

par -w -intstyle ise -ol std -t 1 prescale_counter_map.ncd prescale_counter.ncd
prescale_counter.pcf 


Constraints file: prescale_counter.pcf.
PMSPEC -- Overriding Xilinx file <d:/Xilinx91i/virtex2/data/virtex2.acd> with local file
<d:/Xilinx91i/virtex2/data/virtex2.acd>
Loading device for application Rf_Device from file '2v40.nph' in environment d:\Xilinx91i;d:\Xilinx91i.
   "prescale_counter" is an NCD, version 3.1, device xc2v40, package cs144, speed -6

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)


Device speed data version:  "PRODUCTION 1.121 2006-10-19".


Device Utilization Summary:

   Number of BUFGMUXs                        1 out of 16      6%
   Number of External IOBs                  34 out of 88     38%
      Number of LOCed IOBs                   0 out of 34      0%

   Number of SLICEs                         16 out of 256     6%


Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989713) REAL time: 6 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 6 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 6 secs 

Phase 4.2

Phase 4.2 (Checksum:26259fc) REAL time: 6 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 6 secs 

Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 6 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 6 secs 

Phase 8.8
.
.
.
.
.
.
Phase 8.8 (Checksum:9911c7) REAL time: 12 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 12 secs 

Phase 10.18
Phase 10.18 (Checksum:5f5e0f6) REAL time: 12 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 12 secs 

Phase 12.27
Phase 12.27 (Checksum:7270df4) REAL time: 12 secs 

Phase 13.24
Phase 13.24 (Checksum:7bfa473) REAL time: 12 secs 

REAL time consumed by placer: 12 secs 
CPU  time consumed by placer: 8 secs 
Writing design to file prescale_counter.ncd


Total REAL time to Placer completion: 13 secs 
Total CPU time to Placer completion: 8 secs 

Starting Router

Phase 1: 131 unrouted;       REAL time: 15 secs 

Phase 2: 114 unrouted;       REAL time: 15 secs 

Phase 3: 5 unrouted;       REAL time: 15 secs 

Phase 4: 5 unrouted; (0)      REAL time: 15 secs 

Phase 5: 5 unrouted; (0)      REAL time: 15 secs 

Phase 6: 5 unrouted; (0)      REAL time: 15 secs 

Phase 7: 0 unrouted; (0)      REAL time: 15 secs 

Phase 8: 0 unrouted; (0)      REAL time: 15 secs 


Total REAL time to Router completion: 15 secs 
Total CPU time to Router completion: 9 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |     BUFGMUX7P| No   |   16 |  0.003     |  0.520      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.437
   The MAXIMUM PIN DELAY IS:                               1.236
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.072

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         147          13           0           0           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 5 | SETUP   |     2.325ns|     2.675ns|       0|           0
  0%                                        | HOLD    |     1.117ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  OFFSET = OUT 10 ns AFTER COMP "clk"       | MAXDELAY|     2.914ns|     7.086ns|       0|           0
------------------------------------------------------------------------------------------------------
  TS_upper_counter = MAXDELAY FROM TIMEGRP  | SETUP   |    16.331ns|     3.669ns|       0|           0
  "upper_counter" TO TIMEGRP         "upper |         |            |            |        |            
  _counter" TS_clk * 4                      |         |            |            |        |            
------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 16 secs 
Total CPU time to PAR completion: 10 secs 

Peak Memory Usage:  113 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file prescale_counter.ncd



PAR done!