prescale_counter_map.map

该源码为xilinx ise教程的附带光盘源码

Release 9.1i Map J.30
Xilinx Map Application Log File for Design 'prescale_counter'

Design Information
------------------
Command Line   : d:\Xilinx91i\bin\nt\map.exe -ise
D:/ise_book/Example-5-2/Constraints_Demo/prescale_counter_vhd/prescale_counter_v
hd.ise -intstyle ise -p xc2v40-cs144-6 -cm area -pr b -k 4 -c 100 -tx off -o
prescale_counter_map.ncd prescale_counter.ngd prescale_counter.pcf 
Target Device  : xc2v40
Target Package : cs144
Target Speed   : -6
Mapper Version : virtex2 -- $Revision: 1.36 $
Mapped Date    : Tue Dec 12 15:37:45 2006

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          32 out of     512    6%
  Number of 4 input LUTs:               3 out of     512    1%
Logic Distribution:
  Number of occupied Slices:           16 out of     256    6%
  Number of Slices containing only related logic:      16 out of      16  100%
  Number of Slices containing unrelated logic:          0 out of      16    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:             32 out of     512    6%
  Number used as logic:                 3
  Number used as a route-thru:         29

  Number of bonded IOBs:               34 out of      88   38%
  Number of GCLKs:                      1 out of      16    6%

Total equivalent gate count for design:  451
Additional JTAG gate count for IOBs:  1,632
Peak Memory Usage:  132 MB
Total REAL time to MAP completion:  4 secs 
Total CPU time to MAP completion:   3 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "prescale_counter_map.mrp" for details.