📄 prescale_counter_map.mrp
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Release 9.1i Map J.30Xilinx Mapping Report File for Design 'prescale_counter'Design Information------------------Command Line : d:\Xilinx91i\bin\nt\map.exe -ise
D:/ise_book/Example-5-2/Constraints_Demo/prescale_counter_vhd/prescale_counter_v
hd.ise -intstyle ise -p xc2v40-cs144-6 -cm area -pr b -k 4 -c 100 -tx off -o
prescale_counter_map.ncd prescale_counter.ngd prescale_counter.pcf Target Device : xc2v40Target Package : cs144Target Speed : -6Mapper Version : virtex2 -- $Revision: 1.36 $Mapped Date : Tue Dec 12 15:37:45 2006Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 32 out of 512 6% Number of 4 input LUTs: 3 out of 512 1%Logic Distribution: Number of occupied Slices: 16 out of 256 6% Number of Slices containing only related logic: 16 out of 16 100% Number of Slices containing unrelated logic: 0 out of 16 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 32 out of 512 6% Number used as logic: 3 Number used as a route-thru: 29 Number of bonded IOBs: 34 out of 88 38% Number of GCLKs: 1 out of 16 6%Total equivalent gate count for design: 451Additional JTAG gate count for IOBs: 1,632Peak Memory Usage: 132 MBTotal REAL time to MAP completion: 4 secs Total CPU time to MAP completion: 3 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | IOB | INPUT | LVTTL | | | | | || counter_out<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<16> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<17> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<18> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<19> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<20> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<21> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<22> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<23> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<24> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<25> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<26> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<27> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<28> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<29> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<30> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || counter_out<31> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || reset | IOB | INPUT | LVTTL | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------Area Group Information---------------------- No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration Strings⌨️ 快捷键说明
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