prescale_counter.twr

该源码为xilinx ise教程的附带光盘源码

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Release 9.1i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

d:\Xilinx91i\bin\nt\trce.exe -ise
D:/ise_book/Example-5-2/Constraints_Demo/prescale_counter_vhd/prescale_counter_vhd.ise
-intstyle ise -e 3 -s 6 -xml prescale_counter prescale_counter.ncd -o
prescale_counter.twr prescale_counter.pcf -ucf prescale_counter.ucf

Design file:              prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,package,speed:     xc2v40,cs144,-6 (PRODUCTION 1.121 2006-10-19, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%;

 63 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   2.675ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_upper_counter = MAXDELAY FROM TIMEGRP "upper_counter" TO TIMEGRP
        "upper_counter" TS_clk * 4;

 465 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   3.669ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 10 ns AFTER COMP "clk";

 32 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   7.086ns.
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
---------------+------------+------------------+--------+
               | clk (edge) |                  | Clock  |
Destination    |   to PAD   |Internal Clock(s) | Phase  |
---------------+------------+------------------+--------+
counter_out<0> |    6.840(R)|clk_BUFGP         |   0.000|
counter_out<1> |    7.053(R)|clk_BUFGP         |   0.000|
counter_out<2> |    6.594(R)|clk_BUFGP         |   0.000|
counter_out<3> |    6.334(R)|clk_BUFGP         |   0.000|
counter_out<4> |    6.348(R)|clk_BUFGP         |   0.000|
counter_out<5> |    6.360(R)|clk_BUFGP         |   0.000|
counter_out<6> |    6.803(R)|clk_BUFGP         |   0.000|
counter_out<7> |    6.565(R)|clk_BUFGP         |   0.000|
counter_out<8> |    6.332(R)|clk_BUFGP         |   0.000|
counter_out<9> |    6.349(R)|clk_BUFGP         |   0.000|
counter_out<10>|    7.059(R)|clk_BUFGP         |   0.000|
counter_out<11>|    6.597(R)|clk_BUFGP         |   0.000|
counter_out<12>|    6.593(R)|clk_BUFGP         |   0.000|
counter_out<13>|    6.831(R)|clk_BUFGP         |   0.000|
counter_out<14>|    6.597(R)|clk_BUFGP         |   0.000|
counter_out<15>|    6.827(R)|clk_BUFGP         |   0.000|
counter_out<16>|    6.572(R)|clk_BUFGP         |   0.000|
counter_out<17>|    6.598(R)|clk_BUFGP         |   0.000|
counter_out<18>|    6.831(R)|clk_BUFGP         |   0.000|
counter_out<19>|    6.598(R)|clk_BUFGP         |   0.000|
counter_out<20>|    6.831(R)|clk_BUFGP         |   0.000|
counter_out<21>|    7.058(R)|clk_BUFGP         |   0.000|
counter_out<22>|    6.597(R)|clk_BUFGP         |   0.000|
counter_out<23>|    7.086(R)|clk_BUFGP         |   0.000|
counter_out<24>|    6.593(R)|clk_BUFGP         |   0.000|
counter_out<25>|    7.084(R)|clk_BUFGP         |   0.000|
counter_out<26>|    6.813(R)|clk_BUFGP         |   0.000|
counter_out<27>|    6.803(R)|clk_BUFGP         |   0.000|
counter_out<28>|    6.591(R)|clk_BUFGP         |   0.000|
counter_out<29>|    6.570(R)|clk_BUFGP         |   0.000|
counter_out<30>|    7.052(R)|clk_BUFGP         |   0.000|
counter_out<31>|    6.599(R)|clk_BUFGP         |   0.000|
---------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    3.669|         |         |         |
---------------+---------+---------+---------+---------+

OFFSET = OUT 10 ns AFTER COMP "clk";
Largest slack: 3.668 ns; Smallest slack: 2.914 ns; Relative Skew: 0.754 ns; 
-----------------------------------------------+-------------+-------------+
PAD                                            |    Slack    |Relative Skew|
-----------------------------------------------+-------------+-------------+
counter_out<0>                                 |        3.160|        0.508|
counter_out<1>                                 |        2.947|        0.721|
counter_out<2>                                 |        3.406|        0.262|
counter_out<3>                                 |        3.666|        0.002|
counter_out<4>                                 |        3.652|        0.016|
counter_out<5>                                 |        3.640|        0.028|
counter_out<6>                                 |        3.197|        0.471|
counter_out<7>                                 |        3.435|        0.233|
counter_out<8>                                 |        3.668|        0.000|
counter_out<9>                                 |        3.651|        0.017|
counter_out<10>                                |        2.941|        0.727|
counter_out<11>                                |        3.403|        0.265|
counter_out<12>                                |        3.407|        0.261|
counter_out<13>                                |        3.169|        0.499|
counter_out<14>                                |        3.403|        0.265|
counter_out<15>                                |        3.173|        0.495|
counter_out<16>                                |        3.428|        0.240|
counter_out<17>                                |        3.402|        0.266|
counter_out<18>                                |        3.169|        0.499|
counter_out<19>                                |        3.402|        0.266|
counter_out<20>                                |        3.169|        0.499|
counter_out<21>                                |        2.942|        0.726|
counter_out<22>                                |        3.403|        0.265|
counter_out<23>                                |        2.914|        0.754|
counter_out<24>                                |        3.407|        0.261|
counter_out<25>                                |        2.916|        0.752|
counter_out<26>                                |        3.187|        0.481|
counter_out<27>                                |        3.197|        0.471|
counter_out<28>                                |        3.409|        0.259|
counter_out<29>                                |        3.430|        0.238|
counter_out<30>                                |        2.948|        0.720|
counter_out<31>                                |        3.401|        0.267|
-----------------------------------------------+-------------+-------------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 560 paths, 0 nets, and 144 connections

Design statistics:
   Minimum period:   3.669ns   (Maximum frequency: 272.554MHz)
   Maximum path delay from/to any node:   3.669ns
   Minimum output required time after clock:   7.086ns


Analysis completed Tue Dec 12 15:38:17 2006
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 91 MB