📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity cache is port( clk : in vl_logic; paddr : in vl_logic_vector(7 downto 0); pdata : inout vl_logic_vector(15 downto 0); prw : in vl_logic; pstrb : in vl_logic; prdy : out vl_logic; saddr : out vl_logic_vector(7 downto 0); sdata : inout vl_logic_vector(15 downto 0); srw : out vl_logic; sstrb : out vl_logic; srdy : in vl_logic );end cache;
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