_primary.vhd

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library verilog;
use verilog.vl_types.all;
entity cache_set is
    port(
        addr            : in     vl_logic_vector(7 downto 0);
        data            : inout  vl_logic_vector(15 downto 0);
        hit             : out    vl_logic;
        oen             : in     vl_logic;
        wen             : in     vl_logic
    );
end cache_set;