_primary.vhd

来自「该源码为xilinx ise教程的附带光盘源码」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity memory is
    port(
        clk             : in     vl_logic;
        addr            : in     vl_logic_vector(7 downto 0);
        data            : inout  vl_logic_vector(15 downto 0);
        rw              : in     vl_logic;
        strb            : in     vl_logic;
        rdy             : out    vl_logic
    );
end memory;