i2c.syr

该源码为xilinx ise教程的附带光盘源码

 Number of 4 input LUTs:               194  out of   7168     2%  
 Number of IOs:                         42
 Number of bonded IOBs:                 42  out of    141    29%  
 Number of GCLKs:                        2  out of      8    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 85    |
scl                                | IBUF+BUFG              | 26    |
sda                                | IBUF                   | 2     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-------------------------------------------------------------+----------------------------+-------+
Control Signal                                               | Buffer(FF name)            | Load  |
-------------------------------------------------------------+----------------------------+-------+
I2C_CTRL/I2CDATA_REG/clr_inv(I2C_CTRL/reset_inv1_INV_0:O)    | NONE(I2C_CTRL/scl_in)      | 63    |
uC_CTRL/prs_state_Rst_inv(uC_CTRL/prs_state_Rst_inv1_INV_0:O)| NONE(uC_CTRL/mbdr_micro_2) | 43    |
I2C_CTRL/state_or0000(I2C_CTRL/state_or00001:O)              | NONE(I2C_CTRL/state_FFd1)  | 4     |
I2C_CTRL/detect_stop_or0000(I2C_CTRL/detect_stop_or00001:O)  | NONE(I2C_CTRL/detect_stop) | 1     |
I2C_CTRL/detect_start_or0000(I2C_CTRL/detect_start_or00001:O)| NONE(I2C_CTRL/detect_start)| 1     |
-------------------------------------------------------------+----------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 5.760ns (Maximum Frequency: 173.607MHz)
   Minimum input arrival time before clock: 5.138ns
   Maximum output required time after clock: 8.524ns
   Maximum combinational path delay: 8.817ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.237ns (frequency: 190.944MHz)
  Total number of paths / destination ports: 458 / 92
-------------------------------------------------------------------------
Delay:               5.237ns (Levels of Logic = 3)
  Source:            I2C_CTRL/scl_state_FFd5 (FF)
  Destination:       uC_CTRL/rsta (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: I2C_CTRL/scl_state_FFd5 to uC_CTRL/rsta
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.626   1.078  I2C_CTRL/scl_state_FFd5 (I2C_CTRL/scl_state_FFd5)
     LUT3:I0->O            2   0.479   0.768  I2C_CTRL/rsta_rst11 (N34)
     LUT4_D:I3->LO         1   0.479   0.123  I2C_CTRL/rsta_rst (N790)
     LUT4:I3->O            1   0.479   0.681  uC_CTRL/rsta_not00011 (uC_CTRL/rsta_not0001)
     FDCE:CE                   0.524          uC_CTRL/rsta
    ----------------------------------------
    Total                      5.237ns (2.587ns logic, 2.650ns route)
                                       (49.4% logic, 50.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'scl'
  Clock period: 5.760ns (frequency: 173.607MHz)
  Total number of paths / destination ports: 107 / 24
-------------------------------------------------------------------------
Delay:               5.760ns (Levels of Logic = 3)
  Source:            I2C_CTRL/state_FFd3 (FF)
  Destination:       I2C_CTRL/state_FFd1 (FF)
  Source Clock:      scl falling
  Destination Clock: scl falling

  Data Path: I2C_CTRL/state_FFd3 to I2C_CTRL/state_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           23   0.626   1.741  I2C_CTRL/state_FFd3 (I2C_CTRL/state_FFd3)
     LUT3:I0->O            2   0.479   0.804  I2C_CTRL/state_FFd1-In41 (I2C_CTRL/state_cmp_eq0005)
     LUT3:I2->O            1   0.479   0.976  I2C_CTRL/state_FFd1-In36 (I2C_CTRL/state_FFd1-In_map15)
     LUT4:I0->O            1   0.479   0.000  I2C_CTRL/state_FFd1-In48 (I2C_CTRL/state_FFd1-In)
     FDC_1:D                   0.176          I2C_CTRL/state_FFd1
    ----------------------------------------
    Total                      5.760ns (2.239ns logic, 3.521ns route)
                                       (38.9% logic, 61.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 134 / 67
-------------------------------------------------------------------------
Offset:              5.138ns (Levels of Logic = 4)
  Source:            addr_bus<3> (PAD)
  Destination:       uC_CTRL/cntrl_en (FF)
  Destination Clock: clk rising

  Data Path: addr_bus<3> to uC_CTRL/cntrl_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.715   1.040  addr_bus_3_IBUF (addr_bus_3_IBUF)
     LUT4:I0->O            1   0.479   0.704  uC_CTRL/cntrl_en_mux00021_SW0 (N74)
     LUT4:I3->O            3   0.479   1.066  uC_CTRL/cntrl_en_mux00021 (N50)
     LUT3:I0->O            1   0.479   0.000  uC_CTRL/stat_en_mux00021 (uC_CTRL/stat_en_mux0002)
     FDC:D                     0.176          uC_CTRL/stat_en
    ----------------------------------------
    Total                      5.138ns (2.328ns logic, 2.810ns route)
                                       (45.3% logic, 54.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'scl'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              4.380ns (Levels of Logic = 4)
  Source:            sda (PAD)
  Destination:       I2C_CTRL/state_FFd1 (FF)
  Destination Clock: scl falling

  Data Path: sda to I2C_CTRL/state_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           5   0.715   1.078  sda_IOBUF (N719)
     LUT4_D:I0->LO         1   0.479   0.270  I2C_CTRL/state_FFd2-In21 (N784)
     LUT4:I1->O            1   0.479   0.704  I2C_CTRL/state_FFd1-In13 (I2C_CTRL/state_FFd1-In_map6)
     LUT4:I3->O            1   0.479   0.000  I2C_CTRL/state_FFd1-In48 (I2C_CTRL/state_FFd1-In)
     FDC_1:D                   0.176          I2C_CTRL/state_FFd1
    ----------------------------------------
    Total                      4.380ns (2.328ns logic, 2.052ns route)
                                       (53.2% logic, 46.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'sda'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              1.674ns (Levels of Logic = 1)
  Source:            scl (PAD)
  Destination:       I2C_CTRL/detect_stop (FF)
  Destination Clock: sda rising

  Data Path: scl to I2C_CTRL/detect_stop
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           5   0.715   0.783  scl_IOBUF (N7201)
     FDC:D                     0.176          I2C_CTRL/detect_stop
    ----------------------------------------
    Total                      1.674ns (0.891ns logic, 0.783ns route)
                                       (53.2% logic, 46.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'scl'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.306ns (Levels of Logic = 1)
  Source:            I2C_CTRL/mcf (FF)
  Destination:       mcf (PAD)
  Source Clock:      scl falling

  Data Path: I2C_CTRL/mcf to mcf
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            3   0.626   0.771  I2C_CTRL/mcf (I2C_CTRL/mcf)
     OBUF:I->O                 4.909          mcf_OBUF (mcf)
    ----------------------------------------
    Total                      6.306ns (5.535ns logic, 0.771ns route)
                                       (87.8% logic, 12.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 26 / 12
-------------------------------------------------------------------------
Offset:              8.524ns (Levels of Logic = 3)
  Source:            I2C_CTRL/master_slave (FF)
  Destination:       sda (PAD)
  Source Clock:      clk rising

  Data Path: I2C_CTRL/master_slave to sda
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            14   0.626   1.304  I2C_CTRL/master_slave (I2C_CTRL/master_slave)
     LUT4:I0->O            1   0.479   0.000  I2C_CTRL/sda_oe_inv1 (N765)
     MUXF5:I0->O           1   0.314   0.681  I2C_CTRL/sda_oe_inv_f5 (I2C_CTRL/sda_oe_inv)
     IOBUF:T->IO               5.120          sda_IOBUF (sda)
    ----------------------------------------
    Total                      8.524ns (6.539ns logic, 1.985ns route)
                                       (76.7% logic, 23.3% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay:               8.817ns (Levels of Logic = 3)
  Source:            r_w (PAD)
  Destination:       data_bus<7> (PAD)

  Data Path: r_w to data_bus<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            21   0.715   1.583  r_w_IBUF (r_w_IBUF)
     LUT2:I0->O            8   0.479   0.921  uC_CTRL/data_bus_and0000_inv1 (uC_CTRL/data_bus_and0000_inv)
     IOBUF:T->IO               5.120          data_bus_7_IOBUF (data_bus<7>)
    ----------------------------------------
    Total                      8.817ns (6.314ns logic, 2.503ns route)
                                       (71.6% logic, 28.4% route)

=========================================================================
CPU : 17.63 / 18.42 s | Elapsed : 18.00 / 18.00 s
 
--> 

Total memory usage is 129344 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    9 (   0 filtered)
Number of infos    :    1 (   0 filtered)