i2c.syr

该源码为xilinx ise教程的附带光盘源码

    | Clock              | scl (falling_edge)                             |
    | Reset              | state$or0000 (positive)                        |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <scl_state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 20                                             |
    | Inputs             | 11                                             |
    | Outputs            | 9                                              |
    | Clock              | sys_clk (rising_edge)                          |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | scl_idle                                       |
    | Power Up State     | scl_idle                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <mal>.
    Found 1-bit register for signal <mcf>.
    Found 1-bit register for signal <mif>.
    Found 1-bit register for signal <srw>.
    Found 1-bit register for signal <maas>.
    Found 8-bit register for signal <mbdr_i2c>.
    Found 1-bit register for signal <rxak>.
    Found 1-bit tristate buffer for signal <sda>.
    Found 1-bit tristate buffer for signal <scl>.
    Found 1-bit register for signal <msta_rst>.
    Found 7-bit comparator equal for signal <addr_match$cmp_eq0000> created at line 690.
    Found 1-bit register for signal <arb_lost>.
    Found 1-bit xor2 for signal <arb_lost$xor0000> created at line 225.
    Found 1-bit register for signal <bus_busy>.
    Found 1-bit register for signal <bus_busy_d1>.
    Found 1-bit register for signal <detect_start>.
    Found 1-bit register for signal <detect_stop>.
    Found 1-bit register for signal <gen_start>.
    Found 1-bit register for signal <gen_stop>.
    Found 1-bit register for signal <i2c_header_en>.
    Found 1-bit register for signal <master_sda>.
    Found 1-bit register for signal <master_slave>.
    Found 1-bit register for signal <msta_d1>.
    Found 1-bit register for signal <scl_in>.
    Found 1-bit register for signal <scl_out_reg>.
    Found 1-bit register for signal <sda_in>.
    Found 1-bit register for signal <sda_out_reg>.
    Found 1-bit register for signal <sda_out_reg_d1>.
    Found 1-bit register for signal <shift_reg_en>.
    Found 1-bit register for signal <shift_reg_ld>.
    Found 1-bit register for signal <slave_sda>.
    Found 1-bit register for signal <sm_stop>.
    Found 1-bit register for signal <stop_scl_reg>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred  36 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Tristate(s).
Unit <i2c_control> synthesized.


Synthesizing Unit <i2c>.
    Related source file is "D:/ise_book/Example-10-1/I2C/i2c.vhd".
WARNING:Xst:646 - Signal <mbdr_read> is assigned but never used.
Unit <i2c> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 4-bit up counter                                      : 2
# Registers                                            : 53
 1-bit register                                        : 47
 8-bit register                                        : 6
# Comparators                                          : 1
 7-bit comparator equal                                : 1
# Tristates                                            : 5
 1-bit tristate buffer                                 : 4
 8-bit tristate buffer                                 : 1
# Xors                                                 : 1
 1-bit xor2                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <I2C_CTRL/scl_state> on signal <scl_state[1:7]> with one-hot encoding.
---------------------------
 State         | Encoding
---------------------------
 scl_idle      | 0000001
 start         | 0000010
 scl_low_edge  | 0000100
 scl_low       | 0001000
 scl_high_edge | 0010000
 scl_high      | 0100000
 stop_wait     | 1000000
---------------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <I2C_CTRL/state> on signal <state[1:3]> with gray encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 000
 header     | 001
 ack_header | 011
 rcv_data   | 010
 ack_data   | 111
 xmit_data  | 110
 wait_ack   | 101
------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <uC_CTRL/prs_state> on signal <prs_state[1:2]> with gray encoding.
--------------------------
 State        | Encoding
--------------------------
 idle         | 00
 addr         | 01
 data_trs     | 11
 assert_dtack | 10
--------------------------
Loading device for application Rf_Device from file '3s400.nph' in environment D:\Xilinx91i;d:\Xilinx91i.
WARNING:Xst:1710 - FF/Latch  <madr_0> (without init value) has a constant value of 0 in block <uc_interface>.
WARNING:Xst:2677 - Node <mbdr_read> of sequential type is unconnected in block <uC_CTRL>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 3
# Counters                                             : 2
 4-bit up counter                                      : 2
# Registers                                            : 106
 Flip-Flops                                            : 106
# Comparators                                          : 1
 7-bit comparator equal                                : 1
# Xors                                                 : 1
 1-bit xor2                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2677 - Node <uC_CTRL/mbdr_read> of sequential type is unconnected in block <i2c>.

Optimizing unit <i2c> ...

Optimizing unit <SHIFT8> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c, actual ratio is 3.

Final Macro Processing ...

Processing Unit <i2c> :
INFO:Xst:741 - HDL ADVISOR - A 2-bit shift register was found for signal <uC_CTRL/as_int_d1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <i2c> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 113
 Flip-Flops                                            : 113

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : i2c.ngr
Top Level Output File Name         : i2c
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 42

Cell Usage :
# BELS                             : 208
#      GND                         : 1
#      INV                         : 9
#      LUT2                        : 40
#      LUT2_D                      : 2
#      LUT2_L                      : 1
#      LUT3                        : 41
#      LUT3_D                      : 1
#      LUT3_L                      : 8
#      LUT4                        : 74
#      LUT4_D                      : 5
#      LUT4_L                      : 13
#      MUXCY                       : 3
#      MUXF5                       : 9
#      VCC                         : 1
# FlipFlops/Latches                : 113
#      FDC                         : 21
#      FDC_1                       : 6
#      FDCE                        : 73
#      FDE_1                       : 1
#      FDP                         : 12
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 41
#      IBUF                        : 28
#      IOBUF                       : 10
#      OBUF                        : 1
#      OBUFT                       : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                     101  out of   3584     2%  
 Number of Slice Flip Flops:           113  out of   7168     1%