xst.xmsgs

该源码为xilinx ise教程的附带光盘源码

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<messages>
<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">addr_ready</arg>&gt; is never used or assigned.
</msg>

<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">madr&lt;0&gt;</arg>&gt; is never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">zero_sig</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">i2c_shiftout</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">bit_cnt_clr</arg>&gt; is never used or assigned.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">mbdr_read</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="1710" delta="unknown" >FF/Latch  &lt;<arg fmt="%s" index="1">madr_0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uc_interface</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="unknown" >Node &lt;<arg fmt="%s" index="1">mbdr_read</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uC_CTRL</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2677" delta="unknown" >Node &lt;<arg fmt="%s" index="1">uC_CTRL/mbdr_read</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">i2c</arg>&gt;.
</msg>

<msg type="info" file="Xst" num="741" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">uC_CTRL/as_int_d1</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL<arg fmt="%d" index="5">16</arg> (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

</messages>