load_gen.v

来自「该源码为xilinx ise教程的附带光盘源码」· Verilog 代码 · 共 31 行

module load_gen(
    clk,
    clk4x,
    loadrise,
    loadfall    
    );
    
input clk;
input clk4x;
output loadrise;
output loadfall;
            
VCC  U_vcc  ( .P( w_HI  )  );

//---------------------------------loadrise gen -------------------------------
wire lr0,lr1;
FDC load_FDC1 (.Q(lr0),      .C(clk),   .CLR(loadrise), .D(w_HI));
FDR load_FDR1 (.Q(lr1),      .C(clk4x), .R(loadrise),   .D(lr0));
FDR load_FDR2 (.Q(loadrise), .C(clk4x), .R(loadrise),   .D(lr1));

//---------------------------------loadfall gen--------------------------------
wire lf0,lf1,lf2;
FDC   load_FDC2 (.Q(lf0),      .C(clk),   .CLR(lf2),  .D(w_HI));
LDC_1 load_LDC_1(.Q(lf1),      .G(clk4x), .CLR(lf2),  .D(lf0));
FDR_1 load_FDR_1(.Q(lf2),      .C(clk4x), .R(lf2),    .D(lf1));
FD_1  load_FD_1 (.Q(loadfall), .C(clk4x),             .D(lf2));
         
endmodule

//-----------------------------------end 64 --------------------2002-5-28 16:43