prescale_counter.par

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Release 9.1i par J.30
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

ZHONGXCH::  Tue Dec 05 10:56:02 2006

par -w -intstyle ise -ol std -t 1 prescale_counter_map.ncd prescale_counter.ncd
prescale_counter.pcf 


Constraints file: prescale_counter.pcf.
Loading device for application Rf_Device from file '5vlx30t.nph' in environment D:\Xilinx91i;d:\Xilinx91i.
   "prescale_counter" is an NCD, version 3.1, device xc5vlx30t, package ff665, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "ADVANCED 1.49 2006-10-19".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.

Device Utilization Summary:

   Number of BUFGs                           1 out of 32      3%
   Number of External IOBs                  34 out of 360     9%
      Number of LOCed IOBs                   0 out of 34      0%

   Number of Slice Registers                32 out of 19200   1%
      Number used as Flip Flops             32
      Number used as Latches                 0
      Number used as LatchThrus              0

   Number of Slice LUTS                     33 out of 19200   1%
   Number of Slice LUT-Flip Flop pairs      34 out of 19200   1%


Overall effort level (-ol):   Standard 
Router effort level (-rl):    Standard 

Starting Router

Phase 1: 134 unrouted;       REAL time: 1 mins 35 secs 

Phase 2: 94 unrouted;       REAL time: 1 mins 35 secs 

Phase 3: 2 unrouted;       REAL time: 1 mins 35 secs 

Phase 4: 2 unrouted; (0)      REAL time: 1 mins 35 secs 

Phase 5: 2 unrouted; (0)      REAL time: 1 mins 35 secs 

Phase 6: 0 unrouted; (0)      REAL time: 1 mins 35 secs 

Phase 7: 0 unrouted; (0)      REAL time: 1 mins 35 secs 

Phase 8: 0 unrouted; (0)      REAL time: 1 mins 35 secs 

Phase 9: 0 unrouted; (0)      REAL time: 1 mins 36 secs 

Total REAL time to Router completion: 1 mins 36 secs 
Total CPU time to Router completion: 1 mins 29 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP | BUFGCTRL_X0Y0| No   |   10 |  0.011     |  1.159      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.689
   The MAXIMUM PIN DELAY IS:                               1.482
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.253

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          58          47           0           0           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP   |         N/A|     1.807ns|     N/A|           0
  _BUFGP                                    | HOLD    |     0.437ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 mins 38 secs 
Total CPU time to PAR completion: 1 mins 31 secs 

Peak Memory Usage:  285 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2

Writing design to file prescale_counter.ncd



PAR done!