prescale_counter.twr
来自「该源码为xilinx ise教程的附带光盘源码」· TWR 代码 · 共 94 行
TWR
94 行
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Release 9.1i Trace
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
D:\Xilinx91i\bin\nt\trce.exe -ise
D:/ise_book/EXAMPLE-1-1/prescale_counter_vhd/prescale_counter_vhd.ise -intstyle
ise -e 3 -s 3 -xml prescale_counter prescale_counter.ncd -o
prescale_counter.twr prescale_counter.pcf
Design file: prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,package,speed: xc5vlx30t,ff665,-3 (ADVANCED 1.49 2006-10-19, STEPPING level 0)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clk to Pad
---------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
---------------+------------+------------------+--------+
counter_out<0> | 6.478(R)|clk_BUFGP | 0.000|
counter_out<1> | 6.604(R)|clk_BUFGP | 0.000|
counter_out<2> | 6.461(R)|clk_BUFGP | 0.000|
counter_out<3> | 6.758(R)|clk_BUFGP | 0.000|
counter_out<4> | 6.443(R)|clk_BUFGP | 0.000|
counter_out<5> | 6.442(R)|clk_BUFGP | 0.000|
counter_out<6> | 6.565(R)|clk_BUFGP | 0.000|
counter_out<7> | 6.715(R)|clk_BUFGP | 0.000|
counter_out<8> | 6.632(R)|clk_BUFGP | 0.000|
counter_out<9> | 6.427(R)|clk_BUFGP | 0.000|
counter_out<10>| 6.485(R)|clk_BUFGP | 0.000|
counter_out<11>| 6.596(R)|clk_BUFGP | 0.000|
counter_out<12>| 6.449(R)|clk_BUFGP | 0.000|
counter_out<13>| 6.428(R)|clk_BUFGP | 0.000|
counter_out<14>| 6.570(R)|clk_BUFGP | 0.000|
counter_out<15>| 6.598(R)|clk_BUFGP | 0.000|
counter_out<16>| 6.450(R)|clk_BUFGP | 0.000|
counter_out<17>| 6.451(R)|clk_BUFGP | 0.000|
counter_out<18>| 6.328(R)|clk_BUFGP | 0.000|
counter_out<19>| 6.728(R)|clk_BUFGP | 0.000|
counter_out<20>| 6.584(R)|clk_BUFGP | 0.000|
counter_out<21>| 6.434(R)|clk_BUFGP | 0.000|
counter_out<22>| 6.320(R)|clk_BUFGP | 0.000|
counter_out<23>| 6.435(R)|clk_BUFGP | 0.000|
counter_out<24>| 6.654(R)|clk_BUFGP | 0.000|
counter_out<25>| 6.576(R)|clk_BUFGP | 0.000|
counter_out<26>| 6.563(R)|clk_BUFGP | 0.000|
counter_out<27>| 6.562(R)|clk_BUFGP | 0.000|
counter_out<28>| 6.444(R)|clk_BUFGP | 0.000|
counter_out<29>| 6.593(R)|clk_BUFGP | 0.000|
counter_out<30>| 6.561(R)|clk_BUFGP | 0.000|
counter_out<31>| 6.606(R)|clk_BUFGP | 0.000|
---------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 1.807| | | |
---------------+---------+---------+---------+---------+
Analysis completed Tue Dec 05 10:58:06 2006
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 257 MB
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