prescale_counter.twr

该源码为xilinx ise教程的附带光盘源码

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Release 9.1i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

D:\Xilinx91i\bin\nt\trce.exe -ise
D:/ise_book/Example-1-1/prescale_counter_ver/prescale_counter_ver.ise -intstyle
ise -e 3 -s 3 -xml prescale_counter prescale_counter.ncd -o
prescale_counter.twr prescale_counter.pcf

Design file:              prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,package,speed:     xc5vlx30t,ff665,-3 (ADVANCED 1.49 2006-10-19, STEPPING level 0)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
counter<0>  |    6.478(R)|clk_BUFGP         |   0.000|
counter<1>  |    6.364(R)|clk_BUFGP         |   0.000|
counter<2>  |    6.462(R)|clk_BUFGP         |   0.000|
counter<3>  |    6.441(R)|clk_BUFGP         |   0.000|
counter<4>  |    6.503(R)|clk_BUFGP         |   0.000|
counter<5>  |    6.444(R)|clk_BUFGP         |   0.000|
counter<6>  |    6.564(R)|clk_BUFGP         |   0.000|
counter<7>  |    6.439(R)|clk_BUFGP         |   0.000|
counter<8>  |    6.624(R)|clk_BUFGP         |   0.000|
counter<9>  |    6.444(R)|clk_BUFGP         |   0.000|
counter<10> |    6.553(R)|clk_BUFGP         |   0.000|
counter<11> |    6.599(R)|clk_BUFGP         |   0.000|
counter<12> |    6.431(R)|clk_BUFGP         |   0.000|
counter<13> |    6.451(R)|clk_BUFGP         |   0.000|
counter<14> |    6.720(R)|clk_BUFGP         |   0.000|
counter<15> |    6.441(R)|clk_BUFGP         |   0.000|
counter<16> |    6.582(R)|clk_BUFGP         |   0.000|
counter<17> |    6.457(R)|clk_BUFGP         |   0.000|
counter<18> |    6.485(R)|clk_BUFGP         |   0.000|
counter<19> |    6.615(R)|clk_BUFGP         |   0.000|
counter<20> |    6.455(R)|clk_BUFGP         |   0.000|
counter<21> |    6.448(R)|clk_BUFGP         |   0.000|
counter<22> |    6.604(R)|clk_BUFGP         |   0.000|
counter<23> |    6.436(R)|clk_BUFGP         |   0.000|
counter<24> |    6.482(R)|clk_BUFGP         |   0.000|
counter<25> |    6.447(R)|clk_BUFGP         |   0.000|
counter<26> |    6.318(R)|clk_BUFGP         |   0.000|
counter<27> |    6.590(R)|clk_BUFGP         |   0.000|
counter<28> |    6.477(R)|clk_BUFGP         |   0.000|
counter<29> |    6.443(R)|clk_BUFGP         |   0.000|
counter<30> |    6.436(R)|clk_BUFGP         |   0.000|
counter<31> |    6.557(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    1.918|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Tue Dec 05 15:40:39 2006
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 256 MB