prescale_counter.syr

该源码为xilinx ise教程的附带光盘源码

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : prescale_counter.ngr
Top Level Output File Name         : prescale_counter
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 34

Cell Usage :
# BELS                             : 94
#      GND                         : 1
#      INV                         : 3
#      LUT1                        : 29
#      LUT2                        : 2
#      MUXCY                       : 29
#      VCC                         : 1
#      XORCY                       : 29
# FlipFlops/Latches                : 32
#      FDC                         : 2
#      FDCE                        : 30
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 33
#      IBUF                        : 1
#      OBUF                        : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 5vlx30ff324-3 


Slice Logic Utilization: 
 Number of Slice Registers:             32  out of  19200     0%  
 Number of Slice LUTs:                  34  out of  19200     0%  
    Number used as Logic:               34  out of  19200     0%  

Slice Logic Distribution: 
 Number of Bit Slices used:             34
   Number with an unused Flip Flop       2  out of     34     5%  
   Number with an unused LUT:            0  out of     34     0%  
   Number of fully used Bit Slices:     32  out of     34    94%  

IO Utilization: 
 Number of IOs:                         34
 Number of bonded IOBs:                 34  out of    220    15%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:               1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 32    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
reset_inv(reset_inv1_INV_0:O)      | NONE(counter_0)        | 32    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 2.254ns (Maximum Frequency: 443.558MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 2.509ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 2.254ns (frequency: 443.558MHz)
  Total number of paths / destination ports: 528 / 62
-------------------------------------------------------------------------
Delay:               2.254ns (Levels of Logic = 30)
  Source:            counter_3 (FF)
  Destination:       counter_31 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: counter_3 to counter_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.346   0.753  counter_3 (counter_3)
     LUT1:I0->O            1   0.080   0.000  Madd_counter_31_2_add0000_cy<1>_rt (Madd_counter_31_2_add0000_cy<1>_rt)
     MUXCY:S->O            1   0.260   0.000  Madd_counter_31_2_add0000_cy<1> (Madd_counter_31_2_add0000_cy<1>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<2> (Madd_counter_31_2_add0000_cy<2>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<3> (Madd_counter_31_2_add0000_cy<3>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<4> (Madd_counter_31_2_add0000_cy<4>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<5> (Madd_counter_31_2_add0000_cy<5>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<6> (Madd_counter_31_2_add0000_cy<6>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<7> (Madd_counter_31_2_add0000_cy<7>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<8> (Madd_counter_31_2_add0000_cy<8>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<9> (Madd_counter_31_2_add0000_cy<9>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<10> (Madd_counter_31_2_add0000_cy<10>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<11> (Madd_counter_31_2_add0000_cy<11>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<12> (Madd_counter_31_2_add0000_cy<12>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<13> (Madd_counter_31_2_add0000_cy<13>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<14> (Madd_counter_31_2_add0000_cy<14>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<15> (Madd_counter_31_2_add0000_cy<15>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<16> (Madd_counter_31_2_add0000_cy<16>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<17> (Madd_counter_31_2_add0000_cy<17>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<18> (Madd_counter_31_2_add0000_cy<18>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<19> (Madd_counter_31_2_add0000_cy<19>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<20> (Madd_counter_31_2_add0000_cy<20>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<21> (Madd_counter_31_2_add0000_cy<21>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<22> (Madd_counter_31_2_add0000_cy<22>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<23> (Madd_counter_31_2_add0000_cy<23>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<24> (Madd_counter_31_2_add0000_cy<24>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<25> (Madd_counter_31_2_add0000_cy<25>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<26> (Madd_counter_31_2_add0000_cy<26>)
     MUXCY:CI->O           1   0.021   0.000  Madd_counter_31_2_add0000_cy<27> (Madd_counter_31_2_add0000_cy<27>)
     MUXCY:CI->O           0   0.020   0.000  Madd_counter_31_2_add0000_cy<28> (Madd_counter_31_2_add0000_cy<28>)
     XORCY:CI->O           1   0.262   0.000  Madd_counter_31_2_add0000_xor<29> (counter_31_2_add0000<29>)
     FDCE:D                   -0.024          counter_31
    ----------------------------------------
    Total                      2.254ns (1.501ns logic, 0.753ns route)
                                       (66.6% logic, 33.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              2.509ns (Levels of Logic = 1)
  Source:            counter_0 (FF)
  Destination:       counter_out<0> (PAD)
  Source Clock:      clk rising

  Data Path: counter_0 to counter_out<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   0.346   0.224  counter_0 (counter_0)
     OBUF:I->O                 1.939          counter_out_0_OBUF (counter_out<0>)
    ----------------------------------------
    Total                      2.509ns (2.285ns logic, 0.224ns route)
                                       (91.1% logic, 8.9% route)

=========================================================================
CPU : 39.94 / 40.58 s | Elapsed : 40.00 / 41.00 s
 
--> 

Total memory usage is 288756 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)