prescale_counter.syr

该源码为xilinx ise教程的附带光盘源码

Release 9.1i - xst J.30
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> PMSPEC -- Overriding Xilinx file <d:/Xilinx91i/xbr/data/xbr.acd> with local file <d:/Xilinx91i/xbr/data/xbr.acd>
Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.56 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.56 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: prescale_counter.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "prescale_counter.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "prescale_counter"
Output Format                      : NGC
Target Device                      : xc5vlx30-3-ff324

---- Source Options
Top Module Name                    : prescale_counter
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
power                              : NO
lso                                : prescale_counter.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
async_to_sync                      : NO
use_dsp48                          : auto
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Auto
use_sync_set                       : Auto
use_sync_reset                     : Auto

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/ise_book/Example-5-1/Constraints_Demo/prescale_counter_vhd/prescale_counter.vhd" in Library work.
Architecture behavioral of Entity prescale_counter is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <prescale_counter> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <prescale_counter> in library <work> (Architecture <behavioral>).
Entity <prescale_counter> analyzed. Unit <prescale_counter> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <prescale_counter>.
    Related source file is "D:/ise_book/Example-5-1/Constraints_Demo/prescale_counter_vhd/prescale_counter.vhd".
    Found 32-bit register for signal <counter>.
    Found 2-bit adder for signal <counter_1_0$add0000> created at line 20.
    Found 30-bit adder for signal <counter_31_2$add0000> created at line 30.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <prescale_counter> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 2-bit adder                                           : 1
 30-bit adder                                          : 1
# Registers                                            : 32
 1-bit register                                        : 32

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '5vlx30.nph' in environment d:\Xilinx91i;d:\Xilinx91i.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 2-bit adder                                           : 1
 30-bit adder                                          : 1
# Registers                                            : 32
 Flip-Flops                                            : 32

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <prescale_counter> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block prescale_counter, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 32
 Flip-Flops                                            : 32

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================