prescale_counter.twr

该源码为xilinx ise教程的附带光盘源码

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Release 9.1i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

D:\Xilinx91i\bin\nt\trce.exe -ise
D:/ise_book/Example-5-1/Constraints_Demo/prescale_counter_vhd/prescale_counter_vhd.ise
-intstyle ise -e 3 -s 3 -xml prescale_counter prescale_counter.ncd -o
prescale_counter.twr prescale_counter.pcf -ucf prescale_counter.ucf

Design file:              prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,package,speed:     xc5vlx30,ff324,-3 (ADVANCED 1.49 2006-10-19, STEPPING level 0)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%;

 63 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   1.890ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_upper_counter = MAXDELAY FROM TIMEGRP "upper_counter" TO TIMEGRP
        "upper_counter" TS_clk * 4;

 465 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   1.811ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 10 ns AFTER COMP "clk";

 32 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   6.792ns.
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
---------------+------------+------------------+--------+
               | clk (edge) |                  | Clock  |
Destination    |   to PAD   |Internal Clock(s) | Phase  |
---------------+------------+------------------+--------+
counter_out<0> |    6.471(R)|clk_BUFGP         |   0.000|
counter_out<1> |    6.588(R)|clk_BUFGP         |   0.000|
counter_out<2> |    6.359(R)|clk_BUFGP         |   0.000|
counter_out<3> |    6.618(R)|clk_BUFGP         |   0.000|
counter_out<4> |    6.482(R)|clk_BUFGP         |   0.000|
counter_out<5> |    6.503(R)|clk_BUFGP         |   0.000|
counter_out<6> |    6.493(R)|clk_BUFGP         |   0.000|
counter_out<7> |    6.378(R)|clk_BUFGP         |   0.000|
counter_out<8> |    6.641(R)|clk_BUFGP         |   0.000|
counter_out<9> |    6.589(R)|clk_BUFGP         |   0.000|
counter_out<10>|    6.773(R)|clk_BUFGP         |   0.000|
counter_out<11>|    6.769(R)|clk_BUFGP         |   0.000|
counter_out<12>|    6.499(R)|clk_BUFGP         |   0.000|
counter_out<13>|    6.498(R)|clk_BUFGP         |   0.000|
counter_out<14>|    6.773(R)|clk_BUFGP         |   0.000|
counter_out<15>|    6.373(R)|clk_BUFGP         |   0.000|
counter_out<16>|    6.495(R)|clk_BUFGP         |   0.000|
counter_out<17>|    6.644(R)|clk_BUFGP         |   0.000|
counter_out<18>|    6.485(R)|clk_BUFGP         |   0.000|
counter_out<19>|    6.642(R)|clk_BUFGP         |   0.000|
counter_out<20>|    6.492(R)|clk_BUFGP         |   0.000|
counter_out<21>|    6.641(R)|clk_BUFGP         |   0.000|
counter_out<22>|    6.481(R)|clk_BUFGP         |   0.000|
counter_out<23>|    6.643(R)|clk_BUFGP         |   0.000|
counter_out<24>|    6.492(R)|clk_BUFGP         |   0.000|
counter_out<25>|    6.489(R)|clk_BUFGP         |   0.000|
counter_out<26>|    6.482(R)|clk_BUFGP         |   0.000|
counter_out<27>|    6.740(R)|clk_BUFGP         |   0.000|
counter_out<28>|    6.485(R)|clk_BUFGP         |   0.000|
counter_out<29>|    6.483(R)|clk_BUFGP         |   0.000|
counter_out<30>|    6.736(R)|clk_BUFGP         |   0.000|
counter_out<31>|    6.792(R)|clk_BUFGP         |   0.000|
---------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    1.890|         |         |         |
---------------+---------+---------+---------+---------+

OFFSET = OUT 10 ns AFTER COMP "clk";
Largest slack: 3.641 ns; Smallest slack: 3.208 ns; Relative Skew: 0.433 ns; 
-----------------------------------------------+-------------+-------------+
PAD                                            |    Slack    |Relative Skew|
-----------------------------------------------+-------------+-------------+
counter_out<0>                                 |        3.529|        0.112|
counter_out<1>                                 |        3.412|        0.229|
counter_out<2>                                 |        3.641|        0.000|
counter_out<3>                                 |        3.382|        0.259|
counter_out<4>                                 |        3.518|        0.123|
counter_out<5>                                 |        3.497|        0.144|
counter_out<6>                                 |        3.507|        0.134|
counter_out<7>                                 |        3.622|        0.019|
counter_out<8>                                 |        3.359|        0.282|
counter_out<9>                                 |        3.411|        0.230|
counter_out<10>                                |        3.227|        0.414|
counter_out<11>                                |        3.231|        0.410|
counter_out<12>                                |        3.501|        0.140|
counter_out<13>                                |        3.502|        0.139|
counter_out<14>                                |        3.227|        0.414|
counter_out<15>                                |        3.627|        0.014|
counter_out<16>                                |        3.505|        0.136|
counter_out<17>                                |        3.356|        0.285|
counter_out<18>                                |        3.515|        0.126|
counter_out<19>                                |        3.358|        0.283|
counter_out<20>                                |        3.508|        0.133|
counter_out<21>                                |        3.359|        0.282|
counter_out<22>                                |        3.519|        0.122|
counter_out<23>                                |        3.357|        0.284|
counter_out<24>                                |        3.508|        0.133|
counter_out<25>                                |        3.511|        0.130|
counter_out<26>                                |        3.518|        0.123|
counter_out<27>                                |        3.260|        0.381|
counter_out<28>                                |        3.515|        0.126|
counter_out<29>                                |        3.517|        0.124|
counter_out<30>                                |        3.264|        0.377|
counter_out<31>                                |        3.208|        0.433|
-----------------------------------------------+-------------+-------------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 560 paths, 0 nets, and 95 connections

Design statistics:
   Minimum period:   1.890ns   (Maximum frequency: 529.101MHz)
   Maximum path delay from/to any node:   1.811ns
   Minimum output required time after clock:   6.792ns


Analysis completed Tue Dec 12 16:11:49 2006
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 251 MB