prescale_counter_map.map

该源码为xilinx ise教程的附带光盘源码

Release 9.1i Map J.30
Xilinx Map Application Log File for Design 'prescale_counter'

Design Information
------------------
Command Line   : D:\Xilinx91i\bin\nt\map.exe -ise
D:/ise_book/Example-5-1/Constraints_Demo/prescale_counter_ver/prescale_counter_v
er.ise -intstyle ise -p xc5vlx30t-ff665-3 -w -logic_opt off -ol high -t 1 -cm
area -k 6 -o prescale_counter_map.ncd prescale_counter.ngd prescale_counter.pcf 
Target Device  : xc5vlx30t
Target Package : ff665
Target Speed   : -3
Mapper Version : virtex5 -- $Revision: 1.36 $
Mapped Date    : Tue Dec 12 16:14:38 2006

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:989797) REAL time: 6 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 6 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 6 secs 

Phase 4.33
Phase 4.33 (Checksum:26259fc) REAL time: 1 mins 13 secs 

Phase 5.32
Phase 5.32 (Checksum:2faf07b) REAL time: 1 mins 13 secs 

Phase 6.2
.
Phase 6.2 (Checksum:39386fa) REAL time: 1 mins 14 secs 

Phase 7.30
Phase 7.30 (Checksum:42c1d79) REAL time: 1 mins 14 secs 

Phase 8.3
Phase 8.3 (Checksum:4c4b3f8) REAL time: 1 mins 14 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 1 mins 14 secs 

Phase 10.8
.
.
...............
...............
...............
...............
Phase 10.8 (Checksum:9a180b) REAL time: 1 mins 15 secs 

Phase 11.29
Phase 11.29 (Checksum:68e7775) REAL time: 1 mins 15 secs 

Phase 12.5
Phase 12.5 (Checksum:7270df4) REAL time: 1 mins 15 secs 

Phase 13.18
Phase 13.18 (Checksum:7bfa473) REAL time: 1 mins 15 secs 

Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 1 mins 15 secs 

REAL time consumed by placer: 1 mins 15 secs 
CPU  time consumed by placer: 1 mins 10 secs 
Inspecting route info ...
Route info done.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                    32 out of  19,200    1%
    Number used as Flip Flops:                  32
  Number of Slice LUTs:                         33 out of  19,200    1%
    Number used as logic:                       32 out of  19,200    1%
      Number using O6 output only:               3
      Number using O5 output only:              28
      Number using O5 and O6:                    1
    Number used as exclusive route-thru:         1
  Number of route-thrus:                        29 out of  38,400    1%
    Number using O6 output only:                29

Slice Logic Distribution:
  Number of occupied Slices:                    10 out of   4,800    1%
  Number of LUT Flip Flop pairs used:           33
    Number with an unused Flip Flop:             1 out of      33    3%
    Number with an unused LUT:                   0 out of      33    0%
    Number of fully used LUT-FF pairs:          32 out of      33   96%

  A LUT Flip Flop pair for this architecture represents one LUT paired 
  with one Flip Flop within a slice.  The Slice Logic Distribution
  report is not meaningful if the design is over-mapped for a non-slice
  resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        34 out of     402    8%

Specific Feature Utilization:
  Number of BUFG/BUFGCTRLs:                      1 out of      32    3%
    Number used as BUFGs:                        1

Total equivalent gate count for design:  476
Additional JTAG gate count for IOBs:  1,632
Peak Memory Usage:  353 MB
Total REAL time to MAP completion:  1 mins 54 secs 
Total CPU time to MAP completion:   1 mins 37 secs 

Mapping completed.
See MAP report file "prescale_counter_map.mrp" for details.