📄 prescale_counter.twr
字号:
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Release 9.1i Trace
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
D:\Xilinx91i\bin\nt\trce.exe -ise
D:/ise_book/Example-5-1/Constraints_Demo/prescale_counter_ver/prescale_counter_ver.ise
-intstyle ise -e 3 -s 3 -xml prescale_counter prescale_counter.ncd -o
prescale_counter.twr prescale_counter.pcf -ucf prescale_counter.ucf
Design file: prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,package,speed: xc5vlx30t,ff665,-3 (ADVANCED 1.49 2006-10-19, STEPPING level 0)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%;
63 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 1.695ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_upper_counter = MAXDELAY FROM TIMEGRP "upper_counter" TO TIMEGRP
"upper_counter" TS_clk * 4;
465 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 1.818ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: OFFSET = OUT 10 ns AFTER COMP "clk";
32 items analyzed, 0 timing errors detected.
Minimum allowable offset is 6.768ns.
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
counter<0> | 6.369(R)|clk_BUFGP | 0.000|
counter<1> | 6.477(R)|clk_BUFGP | 0.000|
counter<2> | 6.474(R)|clk_BUFGP | 0.000|
counter<3> | 6.378(R)|clk_BUFGP | 0.000|
counter<4> | 6.549(R)|clk_BUFGP | 0.000|
counter<5> | 6.490(R)|clk_BUFGP | 0.000|
counter<6> | 6.499(R)|clk_BUFGP | 0.000|
counter<7> | 6.379(R)|clk_BUFGP | 0.000|
counter<8> | 6.628(R)|clk_BUFGP | 0.000|
counter<9> | 6.491(R)|clk_BUFGP | 0.000|
counter<10> | 6.654(R)|clk_BUFGP | 0.000|
counter<11> | 6.648(R)|clk_BUFGP | 0.000|
counter<12> | 6.499(R)|clk_BUFGP | 0.000|
counter<13> | 6.505(R)|clk_BUFGP | 0.000|
counter<14> | 6.768(R)|clk_BUFGP | 0.000|
counter<15> | 6.374(R)|clk_BUFGP | 0.000|
counter<16> | 6.628(R)|clk_BUFGP | 0.000|
counter<17> | 6.503(R)|clk_BUFGP | 0.000|
counter<18> | 6.640(R)|clk_BUFGP | 0.000|
counter<19> | 6.662(R)|clk_BUFGP | 0.000|
counter<20> | 6.501(R)|clk_BUFGP | 0.000|
counter<21> | 6.494(R)|clk_BUFGP | 0.000|
counter<22> | 6.764(R)|clk_BUFGP | 0.000|
counter<23> | 6.369(R)|clk_BUFGP | 0.000|
counter<24> | 6.647(R)|clk_BUFGP | 0.000|
counter<25> | 6.618(R)|clk_BUFGP | 0.000|
counter<26> | 6.481(R)|clk_BUFGP | 0.000|
counter<27> | 6.638(R)|clk_BUFGP | 0.000|
counter<28> | 6.611(R)|clk_BUFGP | 0.000|
counter<29> | 6.489(R)|clk_BUFGP | 0.000|
counter<30> | 6.485(R)|clk_BUFGP | 0.000|
counter<31> | 6.484(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 1.818| | | |
---------------+---------+---------+---------+---------+
OFFSET = OUT 10 ns AFTER COMP "clk";
Largest slack: 3.631 ns; Smallest slack: 3.232 ns; Relative Skew: 0.399 ns;
-----------------------------------------------+-------------+-------------+
PAD | Slack |Relative Skew|
-----------------------------------------------+-------------+-------------+
counter<0> | 3.631| 0.000|
counter<1> | 3.523| 0.108|
counter<2> | 3.526| 0.105|
counter<3> | 3.622| 0.009|
counter<4> | 3.451| 0.180|
counter<5> | 3.510| 0.121|
counter<6> | 3.501| 0.130|
counter<7> | 3.621| 0.010|
counter<8> | 3.372| 0.259|
counter<9> | 3.509| 0.122|
counter<10> | 3.346| 0.285|
counter<11> | 3.352| 0.279|
counter<12> | 3.501| 0.130|
counter<13> | 3.495| 0.136|
counter<14> | 3.232| 0.399|
counter<15> | 3.626| 0.005|
counter<16> | 3.372| 0.259|
counter<17> | 3.497| 0.134|
counter<18> | 3.360| 0.271|
counter<19> | 3.338| 0.293|
counter<20> | 3.499| 0.132|
counter<21> | 3.506| 0.125|
counter<22> | 3.236| 0.395|
counter<23> | 3.631| 0.000|
counter<24> | 3.353| 0.278|
counter<25> | 3.382| 0.249|
counter<26> | 3.519| 0.112|
counter<27> | 3.362| 0.269|
counter<28> | 3.389| 0.242|
counter<29> | 3.511| 0.120|
counter<30> | 3.515| 0.116|
counter<31> | 3.516| 0.115|
-----------------------------------------------+-------------+-------------+
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 560 paths, 0 nets, and 95 connections
Design statistics:
Minimum period: 1.818ns (Maximum frequency: 550.055MHz)
Maximum path delay from/to any node: 1.818ns
Minimum output required time after clock: 6.768ns
Analysis completed Tue Dec 12 16:18:32 2006
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 256 MB
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