_primary.vhd

来自「该源码为xilinx ise教程的附带光盘源码」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity \sp_syn_ram-3D\ is
    generic(
        data_width      : integer := 8;
        addr_width      : integer := 3
    );
    port(
        addr            : in     vl_logic_vector;
        data_in         : in     vl_logic_vector;
        inclk           : in     vl_logic;
        outclk          : in     vl_logic;
        we              : in     vl_logic;
        data_out        : out    vl_logic_vector
    );
end \sp_syn_ram-3D\;