color_map.v

该源码为xilinx ise教程的附带光盘源码

// --------------------------------------------------------------------- 
// File     :color_map.v
// Module   :color_map
// Function :This module map certain color for output
// --------------------------------------------------------------------- 
// keywords : 
// ---------------------------------------------------------------------
// Remarks  :System clock is 100MHZ, TFT clock is 25MHZ.
// if resolution is set at 640*480, TFT is 25MHZ to fit the display.
// --------------------------------------------------------------------- 
// History: 
// Version  Date            Author          Description 
// v0.0     2006/08/08      Jiang Zuojie    Original : display 4 vertical color strips
// --------------------------------------------------------------------- 

//==============================================================================
// DEFINE
//==============================================================================
//width for how many bits for one color
`define    Width_bit_color        3 
//for color data transfer through opb bus
`define    Width_opb_databus      9
//the corresponding bits in iColorData
`define    ColorRed               0 : 2
`define    ColorGreen             3 : 5
`define    ColorBlue              6 : 8
module   color_map ( Sys_clk ,
                     Sys_rst ,
                     iColordata ,
                     Enable ,
                     Red ,
                     Green ,
                     Blue
                    );
                    
//==============================================================================
// Port Declaration
//==============================================================================
   input                                         Sys_clk;
   input                                         Sys_rst;//at present,use push button to rst
   input                                         Enable;
   input       [ 0 : `Width_opb_databus - 1 ]    iColordata;
   //--------------------------------------------------------------------------------
   output      [ 0 : `Width_bit_color - 1 ]      Red;//output to port 'R' in top module
   output      [ 0 : `Width_bit_color - 1 ]      Green;//output to port 'R' in top module
   output      [ 0 : `Width_bit_color - 1 ]      Blue;//output to port 'R' in top module
   
//==============================================================================
// Net Declaration
//==============================================================================  
   reg         [ 0 : `Width_bit_color - 1 ]      RedX;//the value of red color in X direction
   reg         [ 0 : `Width_bit_color - 1 ]      GreenX;//the value of green color in X direction
   reg         [ 0 : `Width_bit_color - 1 ]      BlueX;//the value of blue color in X direction
//==============================================================================
// ASSIGNMENT
//==============================================================================	
   assign Red = Enable ? RedX : `Width_bit_color'd0 ; 
   assign Green = Enable ? GreenX : `Width_bit_color'd0 ;
   assign Blue = Enable ? BlueX : `Width_bit_color'd0 ;
   
//==============================================================================
// Implement
//==============================================================================		
	  
   //---------------------------------------------------------------------------
	// 3 regs: RedX GreenX BlueX Control colored strips display on X directon
	//---------------------------------------------------------------------------
   always @ ( posedge Sys_clk )  
      begin
          if ( Sys_rst )
             begin
                 RedX <= 0;
                 GreenX <= 0;
                 BlueX <= 0;
             end
          else
             begin
                 /*RedX <= 3'b111;
                 GreenX <= 3'b000;
                 BlueX <= 3'b000;*/
                 RedX <= iColordata [ `ColorRed ];
                 GreenX <= iColordata [ `ColorGreen ];
                 BlueX <= iColordata [ `ColorBlue ];
             end
      end   
       
endmodule