vga_sync.v

该源码为xilinx ise教程的附带光盘源码

// --------------------------------------------------------------------- 
// File     :vga_sync.v
// Module   :vga_sync
// Function :generate horizontal and vertical synchronize signal for VGA
// output, the system will use DAC, max speed 50MHZ to convert 24bits 
// digit signal to analog signal
// --------------------------------------------------------------------- 
// keywords : 
// ---------------------------------------------------------------------
// Remarks  :
// --------------------------------------------------------------------- 
// History: 
// Version  Date       Author          Description 
// v0.0     2006/      Jiang Zuojie    Original 
//     
// --------------------------------------------------------------------- 

//==============================================================================
// DEFINE
//==============================================================================
// some VGA characters at resolution 800*600*72HZ,
// please refer to data sheet for characters of other resolution and refresh set
//640*480:640
`define    H_pixel       800
//40*480:16
`define    H_front       53
//40*480:48
`define    H_back        61
//540*480:96
`define    H_synctime    120
`define    H_period      `H_pixel+`H_front+`H_back+`H_synctime
//40*480:480
`define    V_pixel       600
//40*480:12
`define    V_front       35
//40*480:31
`define    V_back        21
//40*480:2
`define    V_synctime    6
`define    V_period      `V_pixel+`V_front+`V_back+`V_synctime
//for 640+16+48+96 less than 1024 , set count width to 10
`define    Width_cnt_h   11 
`define    Width_cnt_v   11

module vga_sync ( Tft_clk,
                  //Sys_clk,
                  Sys_rst,
                  Hsync,
                  Vsync,
                  Enable
                );
//==============================================================================
// Port Declaration
//==============================================================================
   input                                         Tft_clk;
   input                                         Sys_rst;//at present,use push button to rst
   //--------------------------------------------------------------------------------
   output                                        Hsync;//
   output                                        Vsync;//59HZ
   output                                        Enable;//
//==============================================================================
// Net Declaration
//==============================================================================  
   reg         [ 0 : `Width_cnt_h - 1 ]          Cnt4h;//counter to record how many dots every line
   reg         [ 0 : `Width_cnt_v - 1 ]          Cnt4v;//counter to record how many dots every line
   reg                                           Hsync;//output horizontal synchronize signal
   reg                                           Vsync;//output horizontal synchronize signal
   reg                                           Enable;//indicate the valid period for data output
   //reg                                           en_Cnt4v;//enable vertical counter to count
   //reg         [ 0 : 1 ]                         state4tft_rst;
//==============================================================================
// Implement
//==============================================================================									
   
   //---------------------------------------------------------------------------
	// 1 reg: cnt4h, record how many dots in one line
	//---------------------------------------------------------------------------
   always @ ( posedge Tft_clk or posedge Sys_rst )  
      begin
          if ( Sys_rst )
             begin
                 Cnt4h <= 0;
             end
          else
             begin
                 if ( Cnt4h < `H_period )
                    begin
                       Cnt4h <= Cnt4h + 1;
                    end 
                 else 
                    begin
                       Cnt4h <= 0;
                    end
             end
      end 
   
   //---------------------------------------------------------------------------
	// 1 reg: cnt4v, record how many lines in one frame
	//---------------------------------------------------------------------------
   always @ ( posedge Hsync or posedge Sys_rst )  
      begin
          if ( Sys_rst )
             begin
                 Cnt4v <= 0;
             end
          else
             begin
                 if ( Cnt4v < `V_period )
                    begin
                       Cnt4v <= Cnt4v + 1;
                    end 
                 else 
                    begin
                       Cnt4v <= 0;
                    end
             end
      end 
      
   //---------------------------------------------------------------------------
	// 1 reg: Hsync, horizontal sync signal
	//---------------------------------------------------------------------------
   always @ ( posedge Tft_clk or posedge Sys_rst )    
      begin
          if ( Sys_rst )
             begin
                 Hsync <= 1;//even rst Hsync is also active
             end
          else
             begin//how to understand the interval time of Hsync:...
                 //if ( Cnt4h >= `H_pixel + `H_front && Cnt4h < `H_pixel + `H_front + `H_synctime )
                 if ( Cnt4h >= 0 && Cnt4h <= `H_synctime )
                    begin
                       Hsync <= 0;
                    end 
                 else 
                    begin
                       Hsync <= 1;
                    end
             end
      end 
      
   //---------------------------------------------------------------------------
	// 1 reg: Vsync, vertical sync signal
	//---------------------------------------------------------------------------
   always @ ( posedge Hsync or posedge Sys_rst )  
      begin
          if ( Sys_rst )
             begin
                 Vsync <= 1;//even rst Hsync is also active
             end
          else
             begin//how to understand the interval time of Hsync:...
                 //if ( Cnt4v >= `V_pixel + `V_front && Cnt4v < `V_pixel + `V_front + `V_synctime )
                 if ( Cnt4v >= 0 && Cnt4v <= `V_synctime )
                    begin
                       Vsync <= 0;
                    end 
                 else 
                    begin
                       Vsync <= 1;
                    end
             end
      end 
   //---------------------------------------------------------------------------
	// 1 reg: Enable
	//---------------------------------------------------------------------------
   always @ ( posedge Tft_clk or posedge Sys_rst )  
      begin
          if ( Sys_rst )
             begin
                 Enable <= 0;//even rst Hsync is also active
             end
          else
             begin//how to understand the interval time of Hsync:...
                 if ( Cnt4h <= `H_synctime + `H_back  || Cnt4h >= `H_synctime + `H_back + `H_pixel || Cnt4v <= `V_synctime + `V_back || Cnt4v >= `V_synctime + `V_back + `V_pixel )
                 //if ( Cnt4h > `H_pixel || Cnt4v > `V_pixel )
                    begin
                       Enable <= 0;
                    end 
                 else 
                    begin
                       Enable <= 1;
                    end
             end
      end  
endmodule