opb_hc164_v2_1_0.mpd

该源码为xilinx ise教程的附带光盘源码

## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and  Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.
###################################################################
##
## Name     : opb_hc164
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN opb_hc164

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER


## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0x80000000, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x100
PARAMETER C_HIGHADDR = 0x800000ff, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR

## Ports
PORT iCLK = OPB_Clk, DIR = I, BUS = SOPB
PORT iRST = OPB_Rst, DIR = I, BUS = SOPB
PORT iOPB_ABUS = OPB_ABus, DIR = I, VEC = [31:0], BUS = SOPB
PORT iOPB_DBUS = OPB_DBus, DIR = I, VEC = [31:0], BUS = SOPB
PORT iOPB_BE = OPB_BE, DIR = I, VEC = [3:0], BUS = SOPB
PORT iOPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
PORT iOPB_SELECT = OPB_select, DIR = I, BUS = SOPB
PORT iOPB_SEQADDR = OPB_seqAddr, DIR = I, BUS = SOPB
PORT oHC_DBUS = Sl_DBus, DIR = O, VEC = [31:0], BUS = SOPB
PORT oHC_XFERACK = Sl_xferAck, DIR = O, BUS = SOPB
PORT oHC_errAck = Sl_errAck, DIR = O, BUS = SOPB
PORT oHC_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
PORT oHC_retry = Sl_retry, DIR = O, BUS = SOPB
PORT oHCCP = "", DIR = O
PORT oHCSI = "", DIR = O

END