add_2bit_module.syr

该源码为xilinx ise教程的附带光盘源码

Release 9.1i - xst J.30
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> PMSPEC -- Overriding Xilinx file <D:/Xilinx91i/xbr/data/xbr.acd> with local file <D:/Xilinx91i/xbr/data/xbr.acd>
Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 1.83 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.84 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: add_2bit_module.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "add_2bit_module.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "add_2bit_module"
Output Format                      : NGC
Target Device                      : xcv50e-6-cs144

---- Source Options
Top Module Name                    : add_2bit_module
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : add_2bit_module.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
async_to_sync                      : NO
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "add_2bit_modult.v" in library work
Module <add_2bit_module> compiled
Module <add_2bit> compiled
No errors in compilation
Analysis of file <"add_2bit_module.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <add_2bit_module> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <add_2bit_module>.
WARNING:Xst:2211 - "add_2bit_modult.v" line 8: Instantiating black box module <add_2bit>.
Module <add_2bit_module> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <add_2bit_module>.
    Related source file is "add_2bit_modult.v".
Unit <add_2bit_module> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file 'v50e.nph' in environment D:\Xilinx91i;D:\Xilinx91i.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <add_2bit_module> ...

Mapping all equations...
WARNING:Xst:2036 - Inserting OBUF on port <cout> driven by black box <add_2bit>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <c<1>> driven by black box <add_2bit>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <c<0>> driven by black box <add_2bit>. Possible simulation mismatch.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block add_2bit_module, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : add_2bit_module.ngr
Top Level Output File Name         : add_2bit_module
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 8

Cell Usage :
# IO Buffers                       : 8
#      IBUF                        : 5
#      OBUF                        : 3
# Others                           : 1
#      add_2bit                    : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v50ecs144-6 

 Number of Slices:                       0  out of    768     0%  
 Number of IOs:                          8
 Number of bonded IOBs:                  8  out of     94     8%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 5.522ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay:               5.522ns (Levels of Logic = 1)
  Source:            u1:cout (PAD)
  Destination:       cout (PAD)

  Data Path: u1:cout to cout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    add_2bit:cout          1   0.000   0.920  u1 (cout_OBUF)
     OBUF:I->O                 4.602          cout_OBUF (cout)
    ----------------------------------------
    Total                      5.522ns (4.602ns logic, 0.920ns route)
                                       (83.3% logic, 16.7% route)

=========================================================================
CPU : 7.34 / 9.38 s | Elapsed : 7.00 / 9.00 s
 
--> 

Total memory usage is 128024 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    0 (   0 filtered)